1.Test for Yield Engineer- Taiwan
2.Physical design for yield designer- Taiwan
3.Process and circuit designer- Taiwan
4.Physical and circuit designer- Taiwan
Candiate with Master&PhD degree from IIT with excellent R&D track record in 22/28nm and UDSM technology is highly preferred.
Location - Taiwan
Package- Will be the best in the semiconductor Industry
work permit- will be taken care by client
Urgency- Immidiate
processing time - 2-3weeksthe potential candidate kindly pass me your resme ASAP to
gopal...@gmail.com /
go...@svcircuit.com
1. Test For yield Designer
Test for yield plays more and more important role in yield ramp up at "client org"
especially for advanced process. Exactly localization of defects can directly contribute to
process learning. The job needs creative and talent designer to overcome traditional
design for test (DFT) limitation and come up with new methodology to help defects
position thus help "client org" in process yield ramp up help "client org" in process yield
ramp up
1. Ph.D. majoring in EE related field ( IIT preferred)
3. Experienced in design for test
4. Good knowledge in new advanced diagnosis tools
- N-detection
- Layout aware diagnosis
- Chain diagnosis
- BIST circuit design
5. Familiar with testers is a bonus both for digital and analog test
6. Good in IC design flow
Kindly pass me your profile immediately to
gopal...@gmail.com /
go...@svcircuit.com for processing to
2.Physical design for yield designer
The role is to implement RTL/netlist to GDS for "client org" advanced qualification
vehicle chips with high complexity, high performance, and low power techniques at
"client org" state-of-the-art technology nodes such as 28/22nm. Optical limitations of
lithography and complex process of strain silicon and HKMG are very difficult in the
advanced technology. Design for Yield is important to overcome the difficulty and help
"client org" process yield ramp up.
1. Ph.D. majoring in EE / CS or related field (IIT preferred)
3. Knowledge in cell-based chip implementation flow and related EDA tools
- Synthesis, DFT, APR, SI, STA, DRC, LVS,Spice-sim
4. Litho, etch and OPC knowledge is a plus
5. Design for test knowledge is a must
6. Programming capability is a must
7. Creativity is a must
8. Good English skill
3.Process and circuit designer
Process variability/mismatch is becoming more and more important, especially in
advanced process.How to cure for it from the integration of process and design is the new
challenge at "client org" . The major responsibility is to implement process monitors in
"client org" Test Vehicle. Also build linkage between variation and process tuning is
another important task
1. Master degree or Ph.D. majoring in EE related field
3. Experienced in mixed mode circuit design, test structure design, Spice simulation and
measurement
4. Good knowledge in device physics, process variation, statistic simulation, etc
5. Layout skill is a plus
6. Analog / testline circuit testing is a plus
4.Physical and circuit designer
The role is to implement RTL/netlist to GDS for "client org" advanced qualification
vehicle chips with high complexity, high performance, and low power techniques at
"client org" state-of-the-art technology nodes such as 28/22nm. It is a big challenge to
implement a high grade chip with leading edge EDA tools and help "client org"
advanced process yield ramp up.
1. Master degree majoring in EE / CS or relatedfield
3. Knowledge in cell-based APR implementation flow and related EDA tools
- Synthesis, DFT, APR, SI, STA, DRC, LVS, Spice-sim
4. Fully-custom circuit design skill is a plus
5. Knowledge of CMOS fabrication flow is a plus
6. Creativity is a must
7. Sense for responsibility, highly motivated and willingness to learn in a fast changing
environment
8. Basic English skill
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Have a good day
Thanks&Regards
Gopalakrishnan Sethuraj
"It is not important to make the right decision,but it is important to make the decision right...That's called ATTITUDE "