RTL & Physical design Engineers Posiiotion in Hyderabad

[Vasu]

FE Design Job Description
Positions Open: Multiple
Location: Hyderabad
The candidate will be responsible for participating in the pre-silicon
block and system level design. The candidate will also be responsible
for Front-End chip implementation including design, synthesis and
execution flows that starts with RTL coding and ends with the delivery
of a netlist package ready for physical design. Responsible for
synthesis, netlist generation, timing and logical equivalency checks,
floorplanning, budgeting, clock methodology and timing constraint
management. Candidate will work in collaboration with Physical Design
Engineers in chip level planning and integrations.
REQUIREMENTS

- At least 7-10+ years experience in complex ASIC Design. Direct
experience in SOC or Graphics/Video is plus.
- Have in depth knowledge of entire design process from Design
specification, defining architecture, micro-architecture, RTL design
and functional verification, synthesis, Physical Design, Timing
closure, Tape-out, and post-Si debug.
- Have hands-on experience in Chiplevel Design/Integration activities.
- Some Physical Design exposure required.
- Should be able to Lead a team, and provide Technical mentoring and
guidance to junior engineers.
- Perform Synthesis and netlisting tasks such as SDC Development, Scan
Insertion, ECO implementation, Formal Verification, etc.
- Some exposure to DFT is a strong plus.
- Work with Physical Design team on Floor Plan, budgeting, timing
closure, Signal Integrity, ECO flows, Power analysis, IO PAD
placement, etc.
- Should have expertise in: Cadence RTL Compiler, Design Compiler,
PrimeTime, Conformal LEC. Good knowledge of datapath compilers is
required.
- Should have proficiency in flow development and scripting.
- Expertise in Perl and Tcl is a must.
- Should be able to work closely with RTL Designers and Backend
Physical Design teams across multiple sites.
- Must have good communication & Analytical thinking skills.
- Knowledge of chip bus interfaces such as AHB and various standard
peripherals & interfaces is a plus.
- Bachelor/Master/ Degree in Electrical or Computer Engineering


Physical Design
Position: SDE/MTS and above
Positions Open: Multiple
Location: Hyderabad
Minimum Exp: 5 years (7+ years preferred)

Key Responsibilities:
The position is for a Physical Design Engineer in the PD group
catering to building the next generation fusion SoCs and discrete
graphics processors. Fusion programs cater to the next gen compute
requirements bringing in CPU, GPU and other functions on an integrated
monolithic die. This position requires interface with large front-end
design teams in US, Canada, Shanghai and India, mentoring new hires
and owing an entire chip or portion of the chip from RTL/gates to
tapeout.

The Physical Design Engineer will be responsible for 1. full chip
activities covering floorplanning, clocking, budgeting, timing,
verification etc., and/or 2. block level physical design activities
which includes: floor planning, placement, scan-reordering, clock tree
synthesis, in place optimization, routing, timing analysis/closure,
ECO tasks (timing, functional, noise based ECOs), design rule checks
(DRC), and Layout vs. Schematic (LVS) checks, low power solution
development etc. In addition to this, he/she will also be
participating in Physical design flow development/upgrade by
continuously working with internal design teams and CAD vendors.
Job Requirements:
• Understanding Verilog HDL
• Understanding Deep Submicron effects such as 90nm and below
• Understanding OCV, DFM, DFY
• Excellent Block level and Full-chip physical design skills
• Self-motivated, leadership skills and experience working with
global teams
• Minimum 5 years of ASIC physical design experience
• Back ground of ASIC Physical Design: Floor planning, Clock Tree
Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal
Integrity closure, physical verification, low power implementation etc
• Hands on experience and expertise in Cadence, Synopsys, Magma or
Mentor Physical Implementation Tools
• Should have participated in a minimum of 3 fullchip tapeouts
Position: Physical Design Manager
Location: Hyderabad
Minimum Exp: 10 years (3+ years management preferred)
Key Responsibilities:
The Physical Design Manager will be responsible for the planning and
execution of all SoC or IP physical design activities for ’s next
generation products. She/he will be responsible for execution of
Physical Design (place and route) duties both at block level, IP/macro
level, as well as chip-level. This includes: floor planning,
placement, scan-reordering, clock tree synthesis, in place
optimization, routing, timing analysis/closure and ECO tasks (timing,
functional, noise based ECOs), design rule checks (DRC), and Logical
vs. Schematic (LVS) checks.
The candidate will:
• Provide technical direction, mentoring, skill development
• Be a forward thinker to improve process and innovation
• Interface with other local and global front end and Physical Design
Managers/Directors to define schedules, resource requirements etc.,
• Provide leadership and direction in crisis
• Interface with front-end ASIC teams to resolve issues and problems
• Responsible for execution of program. Multiple projects on the go.

In addition, strong communication skills and an ability to work in
large groups are essential to being successful. Insight into multi-
site project development will be an asset.
The following aspects are desirable:
• Technical
o Understanding Verilog HDL
o Understanding Deep Submicron effects such as 90nm and below
o Understanding OCV, DFM, DFY
o Excellent Block level and Full-chip physical design skills
o Back ground of all aspects of ASIC Physical Design: Floor planning,
Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and
Signal Integrity closure, physical verification, low power
implementation etc
o Hands on recent or past experience and expertise in Cadence,
Synopsys, Magma or Mentor Physical Implementation Tools
o Understanding of complete SoC development cycle, from architecture
to post-silicon debug preferred
o Should have participated in a minimum of 3 fullchip tapeouts
• Management
o Minimum 3 years of ASIC physical design management experience,
working with global teams
o Self-motivated, conflict resolution skills, and experience working
with global teams across time zones
o Detail oriented and schedule driven
o People management skills as well as technical project management
skills

Regards

Srinivas