Openings in Semiconductor Domain

[Vasu]

Dear group Members

greetings to you , I have pretty good openings with my clients in
Pune,hyd and bangalore, If you are looking out for options Please
share your resume ASAP


Title: ASIC Verification

QLogic, a leading supplier of high performance storage networking
solutions, has an immediate need for ASIC Verification professionals.
In this position you will architect and design test benches and
develop and execute verification plans in simulation and in the lab.

Required Experience:

• BS or MS or equivalent degree in Electrical Engineering, Computer
Engineering or related discipline with 5 to 12 years of experience
• Experience developing and using system or block level complex test
benches as well as writing verification plans and requirements
• Experience implementing directed and random test cases
• Must have experience with Verilog, System Verilog, code and
functional coverage. (OVM/VMM/Formal Verification experience would be
a plus.)
• Excellent written & verbal communications skills
• Experience with industry standard protocol. (PCI Express or Ethernet
would be a plus)
• Object Oriented programming and Perl/shell scripting experience
• Storage and/or Ethernet Industry experience preferred.

Desired Experience:

• Hands on experience in Verilog, System Verilog, Ethernet or PCIe or
other industry standard protocols.

Job Location:
Pune/Bangalore/hyd


2


ASIC Design Engineer

Work Location:Ban/Pune

Requires experience in following areas:

• ASIC Architecture Design
• Verilog RTL Design
• Verilog Simulation/Verification (Conventional, Assertion Based,
Formal)
• RTL Synthesis, Equivalence Checking, Static Timing Analysis
• Design Debug and Validation
• Design Documentation
• Knowledge of PCI Express is a must
• Knowledge of Fibre Channel, Ethernet protocol will be considered
plus
• BS or MS or equivalent degree in Electrical Engineering, Computer
Engineering or related discipline with 10+ years of experience


3.


Title: Design Validation and Test (DVT) Senior Engineer (NIC)


Job Description:
• Design and develop the test plan and test cases based on Market
Requirement Document (MRD), Product Requirement Document (PRD) and
Engineering Functional Specification.
• Participate in review of NIC/TOE design and functions, such as FCoE
and iSCSI, and projects.
• Develop the plan and budget on the test equipments, which include
NIC cards, servers, switches, test harness tools, switch, storage,
tc.
• Provide the gap-analysis in the test coverage and develops the test
cases to bridge the gap.
• Implement process to effectively utilize equipment remotely between
the USA and India locations.
• Have the knowledge and experience on test life cycle, from test
architecture, test design and development, test execution, test report
and bug reports.
• Provide support for field and/or OEM customer regarding to the gap
in the test plan and test cases.

Required Skills:
• 5 to 8 years of experience as a senior QA engineers, and at least
three years as Lead in the test development. Minimum of 6-8 years of
exp with networking protocols like TCP/IP, UDP, ethernet.
• Must have in-depth knowledge on networking, including TCP/IP, UDP
Protocol, device driver, TOE. Knowledge on FC or ISCSI will be a
plus.
• Must have in-depth knowledge in any 2 of the 3 operating systems
listed (1) Linux (RHEL and SuSE), (2) Windows (Windows 2003 and
Windows 2008), (3) VMware ESX.
• Must have a Bachelor's degree in Engineering, Computer Science, or
related discipline.
Job Location:
Pune, India.
Position Type:
Full time/Permanent


4




TITLE: Senior Manager Design Validation & Testing (DVT, SQA)


I. POSITION PURPOSE

Manages the process, tasks, schedules and interdepartmental
disciplines required to design, develop, implement and produce product
test plans and reports for the DVT team based out of India and
coordinates closely with the counter-part and management in the USA.
This includes assisting in the definition of the testing strategy,
defining the product test plan, ensuring the completion of all
applicable tests and arranging appropriate resources. Works closely
with engineering and marketing to insure timely and successful high
quality product release.


II. PRINCIPAL ACCOUNTABILITIES

1. A hands-on technical manager who manages all tasks associated with
Device Verification Testing programs for both hardware and software of
storage and networking products. Is heavily involved in establishing
appropriate test procedures that ensure product reliability.
Maintains a strong sense of urgency and a dedication to bring projects
to completion within appropriate time frames. Must interface with
customers as required to establish, document and complete specific
projects.

2. Develops, implements, monitors and reports on comprehensive
projects. Maintains and publishes detailed schedules. Plans resources
as needed. Adheres to budgetary constraints and foresees opportunities
to improve test methodologies as an on-going basis.

3. Chairs test status and review meetings. Reports regularly to
management or related departments on status and establishes any
process necessary to keep all parties informed. Achieves
organizational agreement on goals, schedules, milestones and
performance.

4. Anticipates and analyzes problems pertaining to product
reliability, schedules, and project cost and takes corrective actions.
Insures visibility of all major issues at the senior management level
and provides recommendations/proposals and plans for corrective
action.

5. Defines clear project roles and responsibilities. Works closely
with project team members to resolve any differences or uncertainties
that may arise. Manages for results, efficiently runs projects and
maintenance of all team members.

6. Assists in the development of program procedures, scheduling
standards, process steps and planning of the program management
discipline as practiced within the company.

7. Plans and manages multiple projects simultaneously. Tracks employee
and financial resources, effectively prioritizing tasks across
multiple projects.


III. NATURE AND SCOPE

Emphasis is placed on product quality, schedules, milestones, and
program costs. Responsible for managing all facets of Design
Verification Test strategies and implementations. Generally performs
independently, planning own programs, defining approaches, and
defining specific job responsibilities and assignments. Provides
functional guidance in the areas of training and direction to
subordinates to ensure strong on-going organizational development.
Must be hands-on.



IV. TECHNICAL KNOWLEDGE, EXPERIENCE, AND SKILLS REQUIRED

• 15-18+ years of experience in managing global test teams spread
across USA and India.
• The most recent 7-10 years should be with a USA Product company in
storage networking domain,
• Ideal candidate will have 5-7 years of experience in the USA with a
storage networking product company
• Incumbents must possess proven analytical ability and a high level
technical background to perform complex research and development work.
Technical leadership ability is required
• Must have a Bachelor's degree in Engineering, Computer Science, or
related discipline.
• Must be familiar with all the current operating systems including
VMware, Windows, Linux, etc. Knowledge of iSCSI, Fibre Channel,
Ethernet and FCoE and peripherals that include RAID, disk and tape
subsystems is essential. Software exposure to boot-code, peripheral
device drivers and management software is required.
• Knowledge of automated program or project management tools,
excellent oral and written communication skills, and the ability to
handle several critical issues simultaneously is required.
• Ability to achieve goals through individuals who are not direct
reports using persuasiveness, tact, logic and personal leadership
traits is also required.

V. PRINCIPAL MANAGEMENT SKILLS REQUIRED

1. Implementing programs with and through others that enhance the
company's business goals. Diplomatic and handles conflicts well.
Anticipates group and interdepartmental problems and takes the
necessary steps to avert them.

2. Develops programs in line with marketing/sales/engineering
activities. The business environment is highly technical and dynamic.
Rapid changes and industry trends may require timely and effective
response by the incumbent.

3. Effectively identifies and assembles necessary project resources
and makes them available when needed. By evaluating resources in all
areas, keep projects on time and within budget.

4. Ability to communicate ideas clearly. Ability to organize and
explain complex topics in easy-to-understand terms and tailor ideas to
audience.


work Location-Pune

5

Title: NSG: Software Device Driver Development Software Engineer
(Linux Kernel, Driver development, OFED, Infiniband, Networking
protocols)

Job Description
Required Skills
Requirements for the position include:
Bachelor's degree in Engineering, Computer Science, or related
discipline, or the equivalent in training and experience, and a
minimum of 6 years related experience in the following areas:
• C/C++
• Strong C coding experience (development is done for both Linux and
VxWorks 5.4, all code is in C)
• Strong understanding of network protocols and scalable algorithms
The following are highly desirable:
• Experience with InfiniBand or another HPC interconnect
• Routing Algorithms
• SM/SMA
• OFED
• IPoIB
• Mesh/Torus and advanced topologies
• Familiarity with User space Linux development and VxWorks
development.
• Understanding of network routing, QOS and reliability
• Ability to use protocol analyzers and debug challenging multi-
threaded and/or asynchronous communications problems.
• Ability to read and understand Linux user and kernel level code
(such as for the Open Fabrics supplied IB stack).
• Experience with XML
• Exposure to network management tools, protocols and APIs.
Job Location
Pune, Maharashtra, India.


Physical design Positions in hyderabad

Physical Design
Position: SDE/MTS and above
Positions Open: Multiple
Location: Hyderabad
Minimum Exp: 5 years (7+ years preferred)

Key Responsibilities:
The position is for a Physical Design Engineer in the AMD PD group
catering to building the next generation fusion SoCs and discrete
graphics processors. Fusion programs cater to the next gen compute
requirements bringing in CPU, GPU and other functions on an integrated
monolithic die. This position requires interface with large front-end
design teams in US, Canada, Shanghai and India, mentoring new hires
and owing an entire chip or portion of the chip from RTL/gates to
tapeout.

The Physical Design Engineer will be responsible for 1. full chip
activities covering floorplanning, clocking, budgeting, timing,
verification etc., and/or 2. block level physical design activities
which includes: floor planning, placement, scan-reordering, clock tree
synthesis, in place optimization, routing, timing analysis/closure,
ECO tasks (timing, functional, noise based ECOs), design rule checks
(DRC), and Layout vs. Schematic (LVS) checks, low power solution
development etc. In addition to this, he/she will also be
participating in Physical design flow development/upgrade by
continuously working with internal design teams and CAD vendors.
Job Requirements:
• Understanding Verilog HDL
• Understanding Deep Submicron effects such as 90nm and below
• Understanding OCV, DFM, DFY
• Excellent Block level and Full-chip physical design skills
• Self-motivated, leadership skills and experience working with
global teams
• Minimum 5 years of ASIC physical design experience
• Back ground of ASIC Physical Design: Floor planning, Clock Tree
Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal
Integrity closure, physical verification, low power implementation etc
• Hands on experience and expertise in Cadence, Synopsys, Magma or
Mentor Physical Implementation Tools
• Should have participated in a minimum of 3 fullchip tapeouts
Position: Physical Design Manager
Location: Hyderabad
Minimum Exp: 10 years (3+ years management preferred)
Key Responsibilities:
The Physical Design Manager will be responsible for the planning and
execution of all SoC or IP physical design activities for AMD’s next
generation products. She/he will be responsible for execution of
Physical Design (place and route) duties both at block level, IP/macro
level, as well as chip-level. This includes: floor planning,
placement, scan-reordering, clock tree synthesis, in place
optimization, routing, timing analysis/closure and ECO tasks (timing,
functional, noise based ECOs), design rule checks (DRC), and Logical
vs. Schematic (LVS) checks.
The candidate will:
• Provide technical direction, mentoring, skill development
• Be a forward thinker to improve process and innovation
• Interface with other local and global front end and Physical Design
Managers/Directors to define schedules, resource requirements etc.,
• Provide leadership and direction in crisis
• Interface with front-end ASIC teams to resolve issues and problems
• Responsible for execution of program. Multiple projects on the go.

In addition, strong communication skills and an ability to work in
large groups are essential to being successful. Insight into multi-
site project development will be an asset.
The following aspects are desirable:
• Technical
o Understanding Verilog HDL
o Understanding Deep Submicron effects such as 90nm and below
o Understanding OCV, DFM, DFY
o Excellent Block level and Full-chip physical design skills
o Back ground of all aspects of ASIC Physical Design: Floor planning,
Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and
Signal Integrity closure, physical verification, low power
implementation etc
o Hands on recent or past experience and expertise in Cadence,
Synopsys, Magma or Mentor Physical Implementation Tools
o Understanding of complete SoC development cycle, from architecture
to post-silicon debug preferred
o Should have participated in a minimum of 3 fullchip tapeouts
• Management
o Minimum 3 years of ASIC physical design management experience,
working with global teams
o Self-motivated, conflict resolution skills, and experience working
with global teams across time zones
o Detail oriented and schedule driven
o People management skills as well as technical project management
skills


Regards

Srinivas

recruite...@gmail.com
sinu...@yahoo.co.in