Low power CPU design flow & CAD dev- DFM aware PD & Methodology development- process migration- Position in TAIWAN....

[Gopalakrishnan Sethuraj]

Friends

Greetings…This is Gopal-Director from SV Circuit, Malaysia, the official Souring partner for one of the Leading Foundry in Taiwan. We are looking for outstanding candidates for the below positions with the UDSM Technology 22/28/45nm experience since our client expanding their existing R&D base in Taiwan in full speed. Potential candidate Kindly pass me your immediately to gopal...@gmail.com / go...@svcircuit.com. Kindly keep it confidential….and you can share it your friends whom will be interested for this positions.

 

This is more of low power CPU design flow and methodology development and Low power PD flow development in DFM aware PD flow development.

 

Candidates from highly welcomed form EDA Industry developing latest Technology & tool flow for power, timing, SI , DFM aware PD.  Master with 8+ exp / PhD with 5+ exp preferred. Senior candidates will be considered for lead level positions.

 

Placement location        –Taiwan

Position                        -- very urgent and need to be filled ASAP.

Work permit                  - will take care by client..
interview                         - 2weeks.
Experience lelvel            - 2-6years. Higher experience will be considered for appropriate   position
Pakcage                       – Will be the best in the semiconductor industry
Type                             -Full time and permanent with our client..

 

 

 

1. CPU Design Flow and Methodology Development (MS/PhD)

      Responsibilities

   -     CPU design methodology development (timing, power, signal

   integrity, etc)

   -  CPU-specific design tools development

      Requirements

   -  Experienced in processor circuit design, or CPU design

   flow/methodology development, or tool development for

   low-power/high-performance design

 

2. Low Power Physical Design, Chip implementation, or Low Power Design Methodology development (MS/PhD, PhD preferred)  - DFM aware PD

      Responsibilities

   -  Low-power chip implementation and flow development

   -  Low-power design methodology research and development for next-gen

   technologies

      Requirements

   -  Experienced in low power design, such as in ASIC chip implementation,

   design methodology development, circuit design, or ultra low power

   research

 

3. Process Migration, or layout migration (MS/Ph.D, PhD preferred)

      Responsibilities

   -  Automated layout migration acorss different process technologies

   -  Design analysis and optimization for the migrated/ported designs

      Requirements

   -  Experienced in layout migration or layout compaction tool

   development, and performance optimization for the migrated designs

 

4. DFM Physical Design, or DFM Design Methodology development (Ph.D)

      Responsibilities

   -  Design for Manufacturing (DFM) methodology development

   -        Design for variability (DFV) for the consideration of

   process-design co-optimization

      Requirements

   -  Experienced in R&D for DFM-aware design, and DFM physical design