ASIC Design Verification for FPGA designers …Step upto ASIC world with SystemVerilog, Assertions & Testbench

[CVC Career]

CVC (www.cvcblr.com) is announcing a new session of its 10-day course
on “FPGA-2-ASIC_DV-with SystemVerilog” - a step-by-step approach to
introduce modern day Design & Verification challenges & solutions for
FPGA designers. It is structured as follows:
• Basic Session
o Comprehensive Functional Verification (CFV)
o SystemVerilog basics (SVB)
• Advanced Session
o ABV Introduction
o SystemVerilog Assertions (SVA)
o Project – develop a real life Protocol IP (PIP)
with SVA
o Verification Using SystemVerilog (VSV)

Course contents:
http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf
http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf

Topic Duration
Comprehensive Functional Verification (including UNIX usage, EDA
tools) 1.5 days
SystemVerilog basics 1 day
Project 0.5 days
SystemVerilog Assertions 2 days
SystemVerilog Testbench 2 days
Project 3.0 days

All the course contents, agenda can be found at http://www.cvcblr.com/program_offering.
It is meticulously prepared with the common expertise of FPGA
designers in mind. Having transformed several FPGA designers into ASIC
Design-Verification engineers at CVC we fully understand the
challenges involved, skills needed etc. The course is structured in a
balanced manner with theory and lab sessions tightly embedded in a
manner that helps in mastering topics learned so far in the course.

Schedule:
Dec 1st week at Bangalore
To attend this class, confirm your registration by sending an email to
trai...@cvcblr.com
Ph: +91-9620209226, +91-80-42134156

Please include the following details in your email:
Name:
Company Name:
Contact Email ID:
Contact Number: