Re: AMBA (Advanced Microcontroller Bus Architecture)

[Satish Devrari]

Hi jatin

I have some suggestions for u 

Q1-:What is boundry cross? And why the boundry cross is set to 1K in AHB protocol?

The 1KB restriction you refer to is not a restriction on maximum slave size but a constraint within AHB that says that a burst must not cross a 1KB boundary. The limit is designed to prevent bursts crossing from one device to another and to give a reasonable trade-off between burst size and efficiency. In practise, this means that a master must ALWAYS break a burst that would otherwise cross the 1KB boundary and restart it with a non-sequential transfer. This is all about boundary cross. HBRUST [2:0] will be responsible for boundry crosss.

Q :- What is point to point connection in AMBA, concept used in AMBA ?

 master and slave both drives signal, now we need a connection to connect master and slave. we use point to point topology to connect signals  .

  Q :- Is it possible to cancel a transfer by bus master?

    i think wait signals is generated by slave , therefore master can not cancel a transfer.

Q:-What is the concept of global HREADY? 

HREADY = 1(If HRESP is low with this than trasfer done and if HRESP High than error in second cycle  )

in HREADY high HTRANS wil change from idl to nonseq, means we will jump in data cycle

HREADY = 0(it will show transfer is pending or error in very first cycle means address phase ) .

Dear  for more detail i m sending u a spec of AHB lite . I hope it will help u .

regards 

satish devrari

On Tue, Apr 23, 2013 at 11:01 PM, jatin7797 <jati...@gmail.com> wrote:

Hi,

AMBA is used as the on chip bus in a SoC (System on Chip) design.

I have some questions about AMBA AHB.

1) What is boundry cross? And why the boundry cross is set to 1K in AHB protocol?

2) What is point to point connection in AMBA, concept used in AMBA ?

3) Is it possible to cancel a transfer by bus master?

4) AMBA is basically used for ASIC design or for FPGA design?

5) What is the concept of global HREADY? (I have read from many sources stating that HREADY is high(1) when transfer has finished on the bus & sometimes driven low(0) to extend a transfer)

Any suggestion & help would be greatly appreciated.

Regards

Jatin

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[Silicon Guru]

Good questions and Good answers..

 

I suggest these question/Answers can be posted to the Facebook group for the benifit of wider audience.

 

[Akshat Gupta]

Dear Jatin,

For your question “Is it possible to cancel a transfer by bus master?” I have something to share

 

There is one way the current transfer is cancelled “ if the HGRANT from arbiter first asserted then removed before the current transfer completes.

This is acceptable because the HGRANT signal is only sampled by masters when HREADY is high

However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY or ERROR response from Slave

 

For HREADY Signal, I have something to say

 

1.       An AHB slave must have the HREADY signal as both an input and an output.

2.       HREADY is required as an output from a slave so that the slave can extend the data phase of a transfer.

3.       HREADY is also required as an input so that the slave can determine when the previously selected slave has completed its final transfer and the first data phase transfer for this slave is about to commence.

4.       Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY signal which is routed to all masters on the AHB and is also fed back to all slaves as the HREADY input.

[Jatin Arora]

Let me thanks for your response. I really appreciate your help.