question on counter:

[Satish Devrari]

Question :-

i made a counter in verilog 

always @(posedge clk)

if (rst)

count <=0 ;

else

count <= count + 1;

pls tell me  is this synchronous counter or asynchronous . is there any effect of rst to make this counter synchronous or asynchronous .

 

[Silicon Guru]

Good question..
This is a Synchronous counter, in all aspects.

The async counters are generally ripple counters, which counts asynchronously.

By adding reset in the sensiticity list you can make another type of sync counter,which can be reset asynchronously.

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[Jatin Arora]

Dear Satish,

This is a synchronous counter.

Here transaction is only depend on the clock.

Regards

Jatin