if i m getting negative set up time in d flip flop what should I do to remove it (in verilog).

[Satish Devrari]

[Akashdeep gautam]

You can reduce the clock frequency/increase the time period. set up time is inversely proportional to the clock period.

 

On Sun, Mar 24, 2013 at 5:31 PM, Satish Devrari <satish...@gmail.com> wrote:

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