arbiter verilog code using state machine

[kanika choudhary]

Hi All,

After understanding the concepts of state machines, finally i have written a code along with the test bench, verified it thoroughly, 

Please find below the code, 

Note;- It is a round-robin arbiter design which is there as a part of our assignment, and functionality is , it has to wait for next request in the increasing order until it gives a grant for that request.   

Let me know your comments if any,

Thanks and Regards,

Kanika 

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Code starts here

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module arbiter_k (req0,req1,req2,req3,gnt0,gnt1,gnt2,gnt3,rst,clk);

  input wire req0,req1,req2,req3,rst,clk;

  output reg gnt0,gnt1,gnt2,gnt3;

  

  reg [2:0] state;

  reg [2:0] nxt_state;

  

  //defining types of states required

  

  parameter [2:0] IDLE=000,    

                  REQ0=001,

                  REQ1=010,

                  REQ2=011,

                  REQ3=100;

                  

                  

    always@(posedge clk)  //for transition of states

  begin

  if(rst)

    state <=IDLE;

  else

   state <= nxt_state;

  end 

always@(state,req0,req1,req2,req3) // conditions for states

begin

  case(state)

   

 IDLE:begin

             

        case({req0,req1,req2,req3})

           4'b0000:nxt_state=IDLE;

           4'b0001:nxt_state=REQ3;

           4'b0010:nxt_state=REQ2;

           4'b0011:nxt_state=REQ2;

           4'b0100:nxt_state=REQ1;

           4'b0101:nxt_state=REQ1;

           4'b0110:nxt_state=REQ1;

           4'b0111:nxt_state=REQ1;

           4'b1000:nxt_state=REQ0;

           4'b1001:nxt_state=REQ0;

           4'b1010:nxt_state=REQ0;

           4'b1011:nxt_state=REQ0;

           4'b1100:nxt_state=REQ0;

           4'b1101:nxt_state=REQ0;

           4'b1110:nxt_state=REQ0;

           4'b1111:nxt_state=REQ0;

         endcase

              end

         REQ0: begin

         if(req0&&((req1||~req1)||(req2||~req2)||(req3||~req3)))

         begin 

             gnt0=1;

             gnt1=0;

             gnt2=0;

             gnt3=0;

             $display($time,"req0 is granted");

         nxt_state=REQ1;

           end

        else

        nxt_state= REQ0;

          end

          REQ1:begin

        if(req1&&((req0||~req0)||(req2||~req2)||(req3||~req3)))

        begin 

             gnt0=0;

             gnt1=1;

             gnt2=0;

             gnt3=0;

             $display($time,"req1 is granted");

             nxt_state=REQ2;

         end

       else

          nxt_state= REQ1;

       end

          REQ2: begin

       if(req2&&((req1||~req1)||(req0||~req0)||(req3||~req3)))

       begin 

             gnt0=0;

             gnt1=0;

             gnt2=1;

             gnt3=0;

             $display($time,"req2 is granted");

             nxt_state=REQ3;

           end

       else

          nxt_state= REQ2;

       end

          REQ3:begin

           if(req3&&((req1||~req1)||(req2||~req2)||(req0||~req0)))

            begin 

             gnt0=0;

             gnt1=0;

             gnt2=0;

             gnt3=1;

             $display($time,"req3 is granted");

             nxt_state=REQ0;

           end

       else

        nxt_state= REQ3;

       end

          default:

          $display($time,"invalid request");

        endcase

      end

endmodule

module test_k();

  reg req0,req1,req2,req3,rst,clk;

  wire gnt0,gnt1,gnt2,gnt3;

   arbiter_k n1(.req0(req0),.req1(req1),.req2(req2),.req3(req3),

               .gnt0(gnt0),.gnt1(gnt1),.gnt2(gnt2),.gnt3(gnt3),.rst(rst),.clk(clk));

  

  always  //generating clock pulses

  #2 clk=~clk;

  

  initial

  begin

    clk=0;

    rst=0;

    #2 rst=1;

    #2 rst=0;

    #500 $finish;

  end

  

   always@(posedge clk) //stimulus generation

   if(rst)

     begin

     req0 <= 1'b0;

     req1 <= 1'b0;

     req2 <= 1'b0;

     req3 <= 1'b0;

   end

   else

   begin

     req0 <= $random;

     req1 <= $random;

     req2 <= $random;

     req3 <= $random;

   end

 

  endmodule

  

[amiit puri]

Thanks and Regards
Amit Puri

[Silicon Guru]

Guys some suggestions:

 

1. When you are writing the module in Verilog it should be written as follows:

 

module <name> (

port1,

port2,

..

..

)

input port1;

output port2;

...

 

endmodule

 

It is easier to maintain and read this code.

 

2. $display statement should not be embedded inside the module . Though it can be part of testbench.

3. testbench should be the top module and should be written in  a separate file.

4. Testcase should be a separate file ( as you may have 100 testcases using the same testbench and to test the same DUT)

5. There should be a separate driver file which should contain the "task".

6. You must write a modular code. Which is easy to understand and easy to maintain and easy too explain.

7. There should be a dedicated tasks for clock generation and reset generation, and also for initialisation of input signals.

 

 

On Tue, Oct 23, 2012 at 1:05 PM, kanika choudhary <kani...@gmail.com> wrote:

[Akshat Gupta]

Hi ,

 

Thanks for your valuable feedback,

Just for your information, Candidates follows the same process mentioned below when they design and verify the major exercises like Sync FIFO design and Timer IP design, also uses tasks,

 

For the smaller codes they follow the simple testbench approach,

 

Rgds,

Akshat

[Silicon Guru]

I feel it is easier to learn the good Industry practices on a smaller design.

 

 Please encourage every one to use the most difficult methods which are used and followed in Industry even if they write the simplest code for counter.

 

Our training objective is not just to teach how to write verilog code. The major Incise differentiator is to teach what Industry is using .. to make each student.. Industry ready.

Excellence is a practice.. not one time show...

Regards

[sri latha]

hi,can i get amba ahb 2.0 specification arbiter code sir...please

[muneeb...@gmail.com]

hi,

Your test bench doesn't seem to work

[lohith vanga]

Miss kanika choudary,

thank you for the code.

Can you please post the FSM of ARBITER(RR)

On Tuesday, October 23, 2012 at 1:05:21 PM UTC+5:30, kanika choudhary wrote: