query

[amiit puri]

Dear all,

              i have a query about setup time and hold time.

              Pls anyone tell me when and why setup time and hold time is needed to necessary and  reliable 

              operation for sequential circuits.

regards 

Amit Puri

[Sanjeeta Das]

Sequential circuit says........it depends upon d present inputs as well as previous outputs so all d inputs should be available to the circuit before it starts it operation at clock edge.

 

Set up time is d time b4 d clock edge where d input needs to b stable in order to b applied properly.

 

Hold time is d time after d clock edge where d signals need to b stable in order to ensure dat it is properly sensed by d circuit.

Otherwise circuit won't b able to detect signal n v vl receive wrong results.

[Silicon Guru]

Good answer Sanjeeta..

 

I would like to add what Sanjeeta has already explained..

 

Actually setup and hold times are the characteristics of the flip flop (FF's )(Sequential ckts). These FFs are designed such that the data should be available some time (setup) before the clock edge and should be stable for some time (hold) after the clock edge. Please note the setup and hold time of the FF's are decided by the designer of those FF.

The typycal values of these ckts in 180nm technology could be 1 to 5ns(setup) 1to -2ns (hold). Worth noting here the hold time could be negative also.

Now with this information I have a question to all students?

 

What happens if hold time violates? How to fix it?

What happens if setup time violates ? how to fix it?

Show pictorially how setup  or hold could violate?

[SANCHIKA AGGARWAL]

Setup Time: the amount of time the synchronous input must be stable before the active edge of the clock.
Hold Time: the amount of time the synchronous input must be stable after the active edge of the clock

If either is violated correct operation of the FF is not guaranteed Metastability can result.

 

Setup time fixing:
1) reducing combinational logic delay by minimising number of logic levels
2) splitting the combinational logic
3) Implimenting Pipelining
4) Using double syncronizer using flipflops

Hold time fixing:
1) Can be fixed by adding delays on input ports (we can use buffers)
2) adjusting clock speed

[SANCHIKA AGGARWAL]

Hi evryone,

I know about setup and hold time but Can anyone tell me how to calculate setup and hold time??

[Silicon Guru]

Hello Sanchika,

  Please go through this article. It explains it very nicely.

http://www.vlsi-expert.com/2011/02/timing-analysis-basis-what-and-why.html

Regards

[Sanchika Aggarwal]

Thank you Sir

--

With warm regards,

SANCHIKA AGGARWAL

PH.- 8860779706

       9250619088

email - sanc...@gmail.com