Paper for Oct. 17th
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Chris Gregg
Oct 13, 2008, 2:31:31 PM10/13/08
to VLSI/Circuits Reading Group
This week's paper will be on the paper entitled, "Robust Energy-
Efficient Adder Topologies:"
http://research.sun.com/vlsi/pubs/04272847.pdf
Abstract: In this paper we explore the relationship between adder
topology and energy efficiency. We compare the energy-delay tradeoff
curves of selected 32-bit adder topologies, to determine how
architectural features and design techniques affect energy efficiency.
Optimizing different adders for the supply and threshold voltages, and
transistor sizing, we show that topologies with the least number of
logic stages having an average fanin of two per stage, and fewest
wires are most energy efficient. While a design with fully custom
sizes can be extremely tedious to layout, we show that custom sizing
can be used as a guide to group different gates in the design,
resulting in a manageable layout overhead without significant loss of
energy efficiency.
-Chris
Efficient Adder Topologies:"
http://research.sun.com/vlsi/pubs/04272847.pdf
Abstract: In this paper we explore the relationship between adder
topology and energy efficiency. We compare the energy-delay tradeoff
curves of selected 32-bit adder topologies, to determine how
architectural features and design techniques affect energy efficiency.
Optimizing different adders for the supply and threshold voltages, and
transistor sizing, we show that topologies with the least number of
logic stages having an average fanin of two per stage, and fewest
wires are most energy efficient. While a design with fully custom
sizes can be extremely tedious to layout, we show that custom sizing
can be used as a guide to group different gates in the design,
resulting in a manageable layout overhead without significant loss of
energy efficiency.
-Chris
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