Hi all,
I am going to lead the discussion at this week's reading group
meeting. We will be reviewing a paper from DSN 02 by Shivakumar et.
al, which talks about the effects of technology scaling and
microarchitectural trends on the soft error rate in CMOS memories and
logic circuits.
http://www.research.ibm.com/arl/publications/papers/dsn02arch.pdf
See you all Friday.
-Nishant
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Nishant George
Graduate Student
Charles L. Brown Department of
Electrical and Computer Engineering
University of Virginia
ni...@virginia.edu