paper for this weeks oct 31 reading

[randy]

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4408785

Abstract
Subthreshold circuit design is promising for future ultralow-energy
sensor applications as well as highly parallel high-performance
processing. Device scaling has the potential to increase speed in
addition to decreasing both energy and cost in subthreshold circuits.
However, no study has yet considered whether device scaling to 45 nm
and beyond will be beneficial for subthreshold logic. We investigate
the implications of device scaling on subthreshold logic and SRAM and
And that the slow scaling of gate-oxide thickness leads to a 60%
reduction in Ion/Ioff between the 90- and 32-nm device generations. We
highlight the effects of this device degradation on noise margins,
delay, and energy. We subsequently propose an alternative scaling
strategy and demonstrate significant improvements in noise margins,
delay, and energy in sub-Vth circuits. Using both optimized and
unoptimized subthreshold device models, we explore the robustness of
scaled subthreshold SRAM. We use a simple variability model and find
that even small memories become unstable at advanced technology nodes.
However, the simple device optimizations suggested in this paper can
be used to improve nominal read noise margins by 64% at the 32-nm node.