D flip flop
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vema lavanya
Sep 8, 2011, 12:08:07 PM9/8/11
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// Verilog code for d flip flop
module shift_reg(q,i,shift,clock);
output q;
input i,shift,clock;
reg[2:0]s;
wire q;
assign q=s[0];
always @(posedge clock)
begin
if(shift==1)
begin
s={i,s[2:1]};
end
end
endmodule
module shift_reg(q,i,shift,clock);
output q;
input i,shift,clock;
reg[2:0]s;
wire q;
assign q=s[0];
always @(posedge clock)
begin
if(shift==1)
begin
s={i,s[2:1]};
end
end
endmodule
vema lavanya
Sep 12, 2011, 1:20:02 AM9/12/11
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// Verilog code for shift regieter
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