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-- VHDL CODE FOR DECODER --------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ---------------------------------------------------
entity Decoder is port ( I: in std_logic_vector (1 downto 0);
O: out std_logic_vector (3 downto 0) ); end Decoder; --------------------------------------------------- architecture behv of Decoder is begin --- Process Statement Process(I) begin
-- use case statement case I is when "00" => O <= "0001";
when "01" => O <= "0010";
when "10" => O <= "0100";
when "11" => O <= "1000";
when others => O <= "xxxx";
end case;
end process;
end behv; -----------------------------------------------
-- Varun D
Varun D
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Sep 8, 2011, 8:12:09 AM9/8/11
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#-------------------------- Basic Script file ------------------------------ #-------------------------- Setting up the environment -------------- set_attribute information_level 7
set root_dir /export/home/user1 set synth_dir $root_dir/results set rtl_path $root_dir/rtl set lib_path $root_dir/com_files set com_fl_path $root_dir/com_files