nclaunch RC JOB1

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Varun D

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Sep 8, 2011, 7:33:33 AM9/8/11
to vlsi_ja...@googlegroups.com
-- VHDL CODE FOR DECODER
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
---------------------------------------------------

entity Decoder is
port ( I: in std_logic_vector (1 downto 0);
        O: out std_logic_vector (3 downto 0)
       );
end Decoder;
---------------------------------------------------
architecture behv of Decoder is
begin
 --- Process Statement
Process(I)
begin
       -- use case statement
case I is
        when "00" => O <= "0001";
        when "01" => O <= "0010";
        when "10" => O <= "0100";
        when "11" => O <= "1000";
        when others => O <= "xxxx";
end case;

end process;

end behv;
-----------------------------------------------



--
Varun D

Varun D

unread,
Sep 8, 2011, 8:12:09 AM9/8/11
to vlsi_jan11_sost
//Verilog code
module Decoder (out,in);
output [3:0]out;
input [1:0] in;
reg [3:0]out;
always @ (in)
begin
       case (in)
                   2'b00: out= 4'b1;
                   2'b01: out= 4'b2;
                   2'b10: out= 4'b4;
                   2'b11: out= 4'b8;
       endcase
end
endmodule

#-------------------------- Basic Script file ------------------------------
#-------------------------- Setting up the environment --------------
set_attribute information_level 7

set root_dir  /export/home/user1
set synth_dir $root_dir/results
set rtl_path $root_dir/rtl
set lib_path $root_dir/com_files
set com_fl_path $root_dir/com_files

set top_module {Decoder}

set_attribute gen_module_prefix G2C_DP_COMP
set_attr hdl_search_path $rtl_path
set_attr lib_search_path $lib_path
set library {typical.lib}
set_attribute library $library

include $com_fl_path /ae_utils.tcl

#------------------------ Loading and Elaborating ------------------
read_hdl com_ckt.v
elaborate $top_module

#------------------------ Synthesizing and writing results ----------------------
synthesize -to_generic
write -g > $synth_dir /generic.v
synthesize -to_mapped
write -mapped > $synth_dir/mapped.v
report gate > $synth_dir/gates.rep
report timing > $synth_dir/timing.rep

--
Varun D




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