some question

[salu]

1. fpga core workng at 100mhz can this core utilize to make 115 or 110
mhz asic and why?
2> %10 a= b blocking
%10 c= d

%10 a<= b non blocking
%10 c<= d

how much time its take for both
3> how c language is different fron vhdl and
verilog...........................
4. one flip flop o/p going to other flip flop.....but combinational
block is there between them whihc is violting setup time fo second flip
flop......without toch this combinational how it can be avioded

[tips_terror]

1.
it can work in asic since fpga LEs are slower than ASIC primitives
2. the blocking statement will take more time ( 20 time stamp)
3.
4. You need to reduce the clock frequency enough to avoid the violation