help required

[salu]

give me ans of these question

diff between signal and variable .......how its synthesisable
advantages and disadvantages between of melay and more
setup and hold time......how it can be overcome....
setuptime and hold time for 0 and 1
where can be use of latch and flip flop
how we can delay ......clock...means take any clock as input....and
output should be same clock but delayed by 2 clock pulses
synchronization,.....data is comingin fast rate.....recevier
side....but catching data at slow rate.....how to synchronize
design ckt divide by 3 with 50% duty cycle

[vlsi-guru]

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