iam doing project called HDLC. In that iam having problem with bit
stuffing. can any one send me the VHDL code for that.
BIT STUFFING:
In the entire data stream, whenaver a string of five consecutive 1's
is detected, this module inserts a '0' after five consecutive 1's to
achive data transparency.
iam doing bit stuffing for 20 bits, so if any one know the logic
behind it please forward to me.