Fwd: Hi Kranthi Kumar........Suresh here
kranthi
From: Suresh <sur...@semiembedded.com>
Date: Fri, Aug 19, 2011 at 6:13 PM
Subject: Hi Kranthi Kumar........Suresh here
To: kranth...@gmail.com
Hi ,
This is Suresh from semiembedded consulting firm, I saw your profile through Linkedin.I am a IT Recruiter from SemiEmbedded Consulting Firm from Bangalore.We have an immediate requirements for Design&Verification Engineers at our clients side.
Our Customers Include :
1. Cisco 2. Beceem 3.
Rambus 4. Infineon 5. Texas Instruments 6. Xilinx 7.
Intel
8. Synapse 9. Wipro 10.Mirafra
11.Qualcomm 12.LSI Logic 13.NXP
and close to 20
Embedded and Semiconductor Startups
If you have any friends looking for a change plz Send me some reference Phone Number or Profile. I will get back to them.
Greetings from Semi Embedded Firm,
Currently we have some excellent , Multiple requirements at Bangalore Location, and I would like to share the requirements here
1.Physical Design Engineer/Lead/Manager who is hands on on following :
Tools : ICC or Talus for PnR , Encounter for FloorPlan , Redhawk for IR
Drop, PT/PTSI , Calibre Activities : Physical design of Hard
Macros/Partitions of sizes upto 1000K placeable instances from
gate-level-Netlist to GDS ,technologies varying from 45nm to 28nm . PD
activities involve , Hard Macro floorplan/IR
Drop/placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS
2. Physical Design Engineer/Lead/Manager who is hands on on following
Tools : Design Compiler , ICC or Talus for PnR , Encounter for FloorPlan ,
Redhawk for IR-Drop, PT/PTSI , Calibre , LEC , Spyglass Activities :
Physical design of Hard Macros/Partitions of sizes upto 1000K placeable
instances from RTLto GDS ,technologies varying from 45nm to 28nm . PD
activities involve , Synthesis of RTL to gate netlist, Netlist level
optimization , RTL to Gate LEC , scan chain hookup ,STA Constraints
management , floorplan/IR-Drop/placement/CTS/Routing/Timing
Optimization/Timing Closure/DRC/LVS .
3. Physical Design - Analog
Skilled Candidates with hands on experience in physical-verification
preferable with analog layout domain.
Experience with calibre rule-writing ,interfacing with foundry is added
advantages
The candidate should have working knowledge of one of the scripting
languages PERLTCL,SHELL,Cadence skill The candidate should have good
aptitude and ready to adapt and learn different domains.
4. STA/Synthesis
Strong Skill in STA/Synthesis with Design Compiler/Prime Time Experience.
Required Experience: 3 to 8 Years' experience
5.ARM Based SOC Verification:
SOC verification exposure (ARM based preferably) using C
. Good command over C language Protocols - AXI/AHB/APB Hands on experience
on the following.System Verilog based oreboard/coverage/regression
development & debug . OVM methodology using System Verilog. . Exposure to
Verilog testbenches and Testcase/regression/coverage development & debug. .
Preferably - Cortex-A9 exposure
Key Words: ARM,Cortex-A9 exposure, command on C language, Protocols -
AXI/AHB/APB
6. RTL Integration.
FE verification (OVM) engineer openings
1. Experience in RTL verification and fundamental knowledge in basic
verification concepts and issues
2. Hands on experience in RTL verification using OVM
3. Development of OVCs using System Verilog
4. Working experience in OVM verification environment building and
integration
5. Developing C/C+ testcases .
6. Working knowledge on ARM based design verification, knowhow of AHB/APB
bus protocols.
RTL Design
1. Verilog/VHDL RTL 2. Synthesis ( DC ) 3. Spyglass ( lint, DFT, PM, CLK/RST )
4. SoC integration flows ( integrating multiple IPs and associated QC )
5. Understanding of Power Management (
voltage domain, power domains, clock domains )
6. OCP and AXI protocols 7. ARM understanding 8. Misc : Debussy, simulators (mti/ncsim ), perl
8. DFT Job Description
Required Skills: Scan insertion, ATPG, Pattern Simulation with and without
timing annotation, Experience on Scan compression techniques, Memory BIST,
Boundary Scan, JTAG concepts, basic understanding of Tester requirements,
basics of synthesis and timing. Knowledge of formal verification. Exposure
to SoC level DFT. Proficiency with Mentor Graphics/Synopsys EDA tools like
Fastscan, Test Kompress, TetraMax, DFTMax, DFTCompiler, DFTAdvisor.
Expertise with memory BIST insertion tools preferably Logic Vision
MBIST/Mentor's MBIST Architect.
Must have good experience with one of the simulation tools -
VCS/Modelsim/NCSim. Good to have knowledge on Debussy/Verdi
9. Analog & Standard Memory cell Layout.
Exp. Required-2-10yrs
DAC, Power Management ICs, PLL, IO Cells, Logic Circuits, Memory Cells etc
Exposure to both Bipolar & CMOS Technolgy
Expertise in Block Level & Full Chip Physical Design Verification
DRC/LVS/RCX)
Expertise in EDA tools for Layout Design Virtuoso, L-Edit, Assura , Calibre
Tapeout Experience of Medium to Large Complex Analog Designs is an advantage
Layout Design
--> Standard Cell / Memory Layouts / Analog & Mixed Signal Layout/ IO Layout/
--> Physical Verification tools like Calibre / Hercules / Assura
Keywords
Characterization ,Standard cell layout, analog layout, IO layout ,layout,Design ,memory, physical design
10. Embedded Systems
Required Skills: strong knowledge in Embedded c/c++, Coding in Embedded C,Review, testing and debugging of codes.
Exp. Required:2-10years
Education Background: Strong education background in BE/B-TECH (ELECTRONICS)
Request you to Please share this email with your friends
Please send Across your updated profile for further process.
Please feel free to reach: sur...@semiembedded.com
-Thanks and Regards
Suresh.