Warm Greetings From Triadss !! We are pleased to let you know that your resume has been found suitable for an opening with our client SiValley, Bangalore/Hubli/Kolkata
Please find below a detailed JD for your reference and kindly send the updated profile. with the following details immediately
Current CTC-
Expected CTC
Joining Period required-
Job Location- Bangalore
Job Description
Analog layout requirement for SERDES IP being done in 7nm. Scope involves scratch layout design.
JD:
• This position requires 3+ Industry experience and has worked on 7nm/10nm analog/custom layout.
• Good understanding of analog concepts along with experience in layout design of complex analog circuits is required.
• Should have worked in Layout of any one of the following is required : Power Management blocks, PLL, PHY, LDO, high performance ADCs, high speed IO’s or Standard cells, integration and taking the block from specification to release.
• Responsibilities will include floor planning, DRC/LVS verification and fix, Reliability Analysis and fix, implementation.
• Should have good debugging skills.
• Hands-on experience with Cadence tools for custom layout.
Qualification: B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics
Looking forward for your reply