set up & hold time

[B. Prasad]

B.Prasad,
Associate Professor,
Electronic Science Department
Kurukshetra University
Kurukshetra
Haryana state-136119
(India)
Cel 09416175523

My blogs,The Quest

"Greatest enemy of KNOWLEDGE is not IGNORANCE but the ILLUSION of knowledge" Stefan Hawkins.

[renu radha]

Very informative document...

On Nov 20, 11:12 am, "B. Prasad" <bprasad2...@gmail.com> wrote:
> B.Prasad,
> Associate Professor,
> Electronic Science Department
> Kurukshetra University
> Kurukshetra
> Haryana state-136119
> (India)
> Cel 09416175523

> My blogs <http://bprasad2010.blogspot.com/>,The
> Quest<http://www.thequestforum.org>

>
> "Greatest enemy of KNOWLEDGE is not IGNORANCE but the ILLUSION of
> knowledge" Stefan Hawkins.
>

>  Setup_n_hold_trainning.pdf
> 278KViewDownload

[Satyanshuu Prakash]

Hi 

First of all thanks for the awesome document .

Is there any other document too  related to the set up and hold time, as there are few thing referred while explaining examples here?  

If yes , then can you please share ti.. i joined this forum today only.. unable to find them.

[nihar soni]

Hello everybody.
I join this group today onward.

This document is very helpful to me that what is setup time and hold time.

But I have a big confusion related to the setup time and hold time violation calculation when in the circuit they give minimum and maximum time.

Then what we have to consider during calculation of setup time and hold time violation and why?

I refer the given document but they didn't mention why the taking the minimum time in some circuit and some circuit maximum time.

[Vineeta]

Hi Nihar,

Let me start by stating 2 things which you would already know:-

1) For setup, the data has to arrive a certain time period before the active edge arrives.

2) For hold, the data has to stay stable for a certain time period after the occurrence of the active edge.

Now while doing STA, we always take the pessimistic approach/ or the worst possible situation.

For setup the worst possible situation is when the delay in the data path is at its worst( i.e the delay is the highest) and the clock path delay is the best (i.e the delay is the least).

Hence while doing setup analysis we consider the maximum delay for data path and minimum delay for clock path.

It would be the vice-verse for hold.

**This is valid while taking the most pessimistic approach, which is generally no so in reality.

Thanks

[Rohit KVSS]

Hi All,

I have a query in GLS .
In timing simulation,if I get any Setup or Hold violation then as a Gls engineer how we should approach ?
By adding delay..if yes how by using Buffers?
Please help me .
Awaiting for your reply.

Regards,
Rohit

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