Verilog Objective Test

[Narveer Yadav]

Hi all,
I have attached verilog objective test with the post. Try to solve it in given time limit. Key for the test will be available on Monday 12 September,2011 at 10:00 AM.

Regards,
Narveer Yadav

[Narveer Yadav]

I have attached the key for verilog objective test. You can post your queries on the forum.
Regards,
Narveer Yadav

[Pardeep]

thanks for the post " verilog objective test"
it is very helpful for us to test our basics and we are expecting some
more posts related to VHDL, Verliog, and Digital in near future.

I want to discuss the three questions ( Q.No. 16, 20 and 25) from the
" verilog objective test"

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Question No. 16

16. Given the following Verilog code, what value of "a" is displayed? 
always @ (clock) begin
a = 0;
a <= 1;
$display(a);
end

A. 0
B. 1
C. either 0 or 1 depending on depending on simulator implementation
D. None of the above


The answer posted is
16. B i.e. the displayed value of a is 1

But when I try to simulate the code then I got the answer 0


// my program is given below

module test_clock(input clock);
integer a;
always @ (clock) begin
a = 0;
a <= 1;
$display(" value of a is %d",a);
end

****************** Simulation Result ************************
# Loading work.test_clock(fast)
force -freeze sim:/test_clock/clock 1 0, 0 {50 ns} -r 100
VSIM 14>run
# value of a is 0
# value of a is 0
# value of a is 0


#################################################################################################################


Question No. 20

20. If time scale is defined as `timescale 10ns/1ns and #1.55 a = b;
then 'a' gets 'b' after
A. 10ns
B. 11 ns
C. 15.5ns
D. 16ns

The answer posted is
20. D i.e. 'a' gets 'b' after 16ns

But when I try to simulate the code then I got the answer 2ns

`timescale 10ns/1ns
module time_scale;
integer a=7,b=5;
initial
begin
#1.55 a = b;
$display(" At time_value of %d \t the value of \n a = %d\n b = %d",
$time,a,b);
end

*************** Simulation Result ****************

VSIM 19>run
# At time_value of 2 the value of
# a = 5
# b = 5






############################################################################################################


25. Variable and signal which will be updated first?
A. Variable
B. Signal
C. Can’t say
D. None of the above

The answer posted for Question 25. B i.e. Signal will be
updated first

But signal and variable terms are used in VHDL and there the
value to variable is assigned in zero delay time
and the value to signal is assigned after some delta delay
time or some finite delay time.



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So, Justify your Answers for Q.No. 16, 20 and 25

[Narveer Yadav]

16.This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:

  1: Active Events (blocking statements)
  2: Inactive Events (#0 delays, etc)
  3: Non-Blocking Assign Updates (non-blocking statements)
  4: Monitor Events ($display, $monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue". The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display statement is placed into the 4th queue.
Only events in the active queue are completed this simulation cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next simulation cycle, it would show 1.

20. When we define `timescale 10ns/1ns.
      10ns represents the reference time and 1ns as precision value. Delays in verilog are multiples of time_unit rounded to time_precision. Here time_unit is 10ns. So 'a' gets 'b' after 16 ns because 10ns*1.55 = 15.5 ns = 16ns rounded to nearest 1ns.

25. What you said is true for VHDL. But in verilog signal are updated first.

[Rohit Kumar K]

Narveer !!!!!! Great man u r doing a very gud job of posting q's and ans also ...If possible please give some interview questions related to Verilog ..

[omprakash choudhary]

sir question no 14

how it take value   of a and b only 0and 1 ? according to me it is race around condition in this condition it will take value a=1 or 2 or b=1 or 2..........................how its taking 0 and 1??

14. Initial value of a=1 and b=2, then what will be final value if

always @ (posedge clock)

a=b;

always @ (posedge clock)

b=a;

A. a= 2, b=1

B. a= 1, b=2

C. Both a and b will have same value either 0 or 1