| Experience required for the Job: 2 - 7 years Annual Salary of the Job: 6.00 - 30.00 Lacs
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Dear Narendra Jaiprakash Mane,
We have an opening in Cadence at Bangalore/Pune/Ahmedabad location for Verification.
If you are interested, please share your updated resume at ri...@assurehrlabs.com .
Cadence Design Systems (India) Pvt. Ltd
Job title: Lead Engineer
Job Location: Bangalore
Job Description
This position requires the development and verification of Verification IPs for various standards specifications.
● Developing performance optimized VIPs for latest (draft/ballot) specifications of various protocols and interfaces.
● Verifying the VIPs for proper functionality and system scenarios (including erroneous conditions)
● Developing test suite and compliance test suite for 100% functional coverage for a given specification.
● Documenting the design and implementation for engineering details and for customers.
● Interacting with internal and external customers and resolving issues in a timely manner.
Required Skills
• • Good working knowledge of various verification concepts such as Verification architecture, coverage, checkers, test plan etc.
• • Strong in building Verification environments based on UVM, System Verilog
• • Should have participated in building IP/full chip verification environments, verification planning and closure process.
• • Domain expertise in NVMe, SAS, SATA, WiFi, Bluetooth, DFI, DDR/LPDDR, PCIe, Flash would be a strong plus
• • Programming skills: C, Verilog, System Verilog mandatory. C++ would be a strong plus.
• • Very good debugging and analytical skills
• • Should have good communication skills and should be a good team player
• • 4+ years of relevant experience
Job Location: Pune
DESIGN VERIFICATION GROUP:
Position Description:
• As a member of the Design Verification Team for Xtensa processors you will be responsible for verification of microprocessor cores and their peripherals.
• Under the mentor-ship of a verification designer, you will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
• You will also assist with developing test plans, debugging failures and analyzing coverage information.
• You will work closely with the RTL and EDA teams.
Required Skills and Experience:
• BS (or higher) in EE/Computer Engineering
• 2-10 Years
• Excellent knowledge of computer architecture and design verification fundamentals
• Some experience with Verilog and popular EDA simulation, SystemVerilog and testbench methodologies
• Exposure to scripting languages like Perl, Unix shell or similar languages
• Some experience with assembly language programming required
Good written and oral communication skills necessary
Job Location: Ahmedabad
Job Description
This position requires the development and verification of Verification IPs for various standards specifications.
● Developing performance optimized VIPs for latest (draft/ballot) specifications of various protocols and interfaces.
● Verifying the VIPs for proper functionality and system scenarios (including erroneous conditions)
● Developing test suite and compliance test suite for 100% functional coverage for a given specification.
● Documenting the design and implementation for engineering details and for customers.
● Interacting with internal and external customers and resolving issues in a timely manner.
Required Skills
• • Good working knowledge of various verification concepts such as Verification architecture, coverage, checkers, test plan etc.
• • Strong in building Verification environments based on UVM, System Verilog
• • Should have participated in building IP/full chip verification environments, verification planning and closure process.
• • Domain expertise in NVMe, SAS, SATA, WiFi, Bluetooth, DFI, DDR/LPDDR, PCIe, Flash would be a strong plus
• • Programming skills: C, Verilog, System Verilog mandatory. C++ would be a strong plus.
• • Very good debugging and analytical skills
• • Should have good communication skills and should be a good team player
• • 2 to 6 years of relevant experience
Thanks & Regards
Rimpa Dutta
Assure HRLabs
Hyderabad
You are receiving this e-mail because your profile contained one or more of the following words that the recruiter searched on: " uvm ", " verilog ", " ovm ", " "system verilog" ", " Verification "
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