[vim/vim] Add SystemVerilog keywords for matchit plugin (#8195)

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HsuehMin Chen

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May 10, 2021, 2:14:04 PM5/10/21
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Vim's matchit plugin cannot match some SystemVerilog keywords like class/endclass due to missing config. This PR aims to support it.


You can view, comment on, or merge this pull request online at:

  https://github.com/vim/vim/pull/8195

Commit Summary

  • Add SystemVerilog keywords for matchit plugin

File Changes

Patch Links:


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HsuehMin Chen

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May 10, 2021, 2:16:16 PM5/10/21
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Related to neovim/neovim#14505

Dominique Pellé

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May 10, 2021, 3:23:22 PM5/10/21
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@dpelle commented on this pull request.


In runtime/ftplugin/systemverilog.vim:

> @@ -1,11 +1,38 @@
 " Vim filetype plugin file
 " Language:    SystemVerilog
 " Maintainer:  kocha <kocha.ls...@gmail.com>

Thanks. Have you emailed the current maintainer?

Kocha

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May 11, 2021, 5:25:23 AM5/11/21
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@Kocha commented on this pull request.


In runtime/ftplugin/systemverilog.vim:

>  
 if exists("b:did_ftplugin")
   finish
 endif
 
 " Behaves just like Verilog
 runtime! ftplugin/verilog.vim
+
+" Add SystemVerilog keywords for matchit plugin.
+if exists("loaded_matchit")
+  let b:match_words =
+    \ '\<begin\>:\<end\>,' .
+    \ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' .
+    \ '\<module\>:\<endmodule\>,' .
+    \ '\<if\>:`\@<!\<else\>,' .
+    \ '\<function\>:\<endfunction\>,' .
+    \ '`ifn\?def\>:`elsif\>:`else\>:`endif\>,' .
+    \ '\<task\>:\<endtask\>,' .
+    \ '\<specify\>:\<endspecify\>,' .
+    \ '\<config\>:\<endconfig\>,' .
+    \ '\<generate\>:\<endgenerate\>,' .
+    \ '\<fork\>:\<join\>,' .

Add join_any and join_none

'\<fork\>:\<join\>\|\<join_any\>\|\<join_none\>,'

HsuehMin Chen

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May 11, 2021, 12:47:57 PM5/11/21
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@elsdrium pushed 1 commit.

  • 277783d Add SystemVerilog keywords, fork and join/join_any/join_none, for matchit plugin


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HsuehMin Chen

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May 11, 2021, 12:53:38 PM5/11/21
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@elsdrium commented on this pull request.


In runtime/ftplugin/systemverilog.vim:

>  
 if exists("b:did_ftplugin")
   finish
 endif
 
 " Behaves just like Verilog
 runtime! ftplugin/verilog.vim
+
+" Add SystemVerilog keywords for matchit plugin.
+if exists("loaded_matchit")
+  let b:match_words =
+    \ '\<begin\>:\<end\>,' .
+    \ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' .
+    \ '\<module\>:\<endmodule\>,' .
+    \ '\<if\>:`\@<!\<else\>,' .
+    \ '\<function\>:\<endfunction\>,' .
+    \ '`ifn\?def\>:`elsif\>:`else\>:`endif\>,' .
+    \ '\<task\>:\<endtask\>,' .
+    \ '\<specify\>:\<endspecify\>,' .
+    \ '\<config\>:\<endconfig\>,' .
+    \ '\<generate\>:\<endgenerate\>,' .
+    \ '\<fork\>:\<join\>,' .

My last commit 277783d added it.

HsuehMin Chen

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May 11, 2021, 12:59:04 PM5/11/21
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@elsdrium pushed 1 commit.

  • 4699600 Add SystemVerilog keywords, fork and join/join_any/join_none, for matchit plugin


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HsuehMin Chen

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May 11, 2021, 1:00:48 PM5/11/21
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@elsdrium commented on this pull request.


In runtime/ftplugin/systemverilog.vim:

>  
 if exists("b:did_ftplugin")
   finish
 endif
 
 " Behaves just like Verilog
 runtime! ftplugin/verilog.vim
+
+" Add SystemVerilog keywords for matchit plugin.
+if exists("loaded_matchit")
+  let b:match_words =
+    \ '\<begin\>:\<end\>,' .
+    \ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' .
+    \ '\<module\>:\<endmodule\>,' .
+    \ '\<if\>:`\@<!\<else\>,' .
+    \ '\<function\>:\<endfunction\>,' .
+    \ '`ifn\?def\>:`elsif\>:`else\>:`endif\>,' .
+    \ '\<task\>:\<endtask\>,' .
+    \ '\<specify\>:\<endspecify\>,' .
+    \ '\<config\>:\<endconfig\>,' .
+    \ '\<generate\>:\<endgenerate\>,' .
+    \ '\<fork\>:\<join\>,' .

Thank you! My last commit 4699600 fixes it.

Kocha

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May 11, 2021, 8:13:12 PM5/11/21
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@Kocha commented on this pull request.


In runtime/ftplugin/systemverilog.vim:

>  

 if exists("b:did_ftplugin")

   finish

 endif

 

 " Behaves just like Verilog

 runtime! ftplugin/verilog.vim

+

+" Add SystemVerilog keywords for matchit plugin.

+if exists("loaded_matchit")

+  let b:match_words =

+    \ '\<begin\>:\<end\>,' .

+    \ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' .

+    \ '\<module\>:\<endmodule\>,' .

+    \ '\<if\>:`\@<!\<else\>,' .

+    \ '\<function\>:\<endfunction\>,' .

+    \ '`ifn\?def\>:`elsif\>:`else\>:`endif\>,' .

+    \ '\<task\>:\<endtask\>,' .

+    \ '\<specify\>:\<endspecify\>,' .

+    \ '\<config\>:\<endconfig\>,' .

+    \ '\<generate\>:\<endgenerate\>,' .

+    \ '\<fork\>:\<join\>,' .

LGTM 👍

codecov[bot]

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May 12, 2021, 5:56:53 AM5/12/21
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Codecov Report

Merging #8195 (4699600) into master (68db996) will decrease coverage by 86.88%.
The diff coverage is n/a.

Impacted file tree graph

@@             Coverage Diff             @@

##           master    #8195       +/-   ##

===========================================

- Coverage   89.35%    2.46%   -86.89%     

===========================================

  Files         148      146        -2     

  Lines      166808   161671     -5137     

===========================================

- Hits       149051     3990   -145061     

- Misses      17757   157681   +139924     
Flag Coverage Δ
huge-clang-none ?
huge-gcc-none ?
huge-gcc-testgui ?
huge-gcc-unittests 2.46% <ø> (ø)

Flags with carried forward coverage won't be shown. Click here to find out more.

Impacted Files Coverage Δ
src/sha256.c 0.00% <0.00%> (-97.96%) ⬇️
src/digraph.c 0.00% <0.00%> (-97.78%) ⬇️
src/gui_gtk_f.c 0.00% <0.00%> (-97.54%) ⬇️
src/match.c 0.00% <0.00%> (-97.13%) ⬇️
src/crypt_zip.c 0.00% <0.00%> (-97.06%) ⬇️
src/evalbuffer.c 0.00% <0.00%> (-96.83%) ⬇️
src/debugger.c 0.00% <0.00%> (-96.62%) ⬇️
src/libvterm/src/rect.h 0.00% <0.00%> (-96.56%) ⬇️
src/textprop.c 0.00% <0.00%> (-96.41%) ⬇️
src/evalfunc.c 0.00% <0.00%> (-96.19%) ⬇️
... and 134 more

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HsuehMin Chen

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May 12, 2021, 10:00:25 AM5/12/21
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@elsdrium commented on this pull request.


In runtime/ftplugin/systemverilog.vim:

> @@ -1,11 +1,38 @@
 " Vim filetype plugin file
 " Language:    SystemVerilog
 " Maintainer:  kocha <kocha.ls...@gmail.com>

@dpelle
Yes. What's the next step? Thanks

Dominique Pellé

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May 12, 2021, 10:18:13 AM5/12/21
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@dpelle commented on this pull request.


In runtime/ftplugin/systemverilog.vim:

> @@ -1,11 +1,38 @@
 " Vim filetype plugin file
 " Language:    SystemVerilog
 " Maintainer:  kocha <kocha.ls...@gmail.com>

Yes, what's the next step?

All good on your side then. And I see that the mainainer @Kocha commented and approved the review.

Bram Moolenaar

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May 13, 2021, 12:58:10 PM5/13/21
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I'll include it, thanks.

Bram Moolenaar

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May 13, 2021, 12:58:10 PM5/13/21
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Closed #8195.

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