Specify defines to verible-verilog-syntax

[Stefan Rystedt]

Hi!

I am trying to get an list off all the  included files recursively from an System Verilog top file which is not something that you support directly as I can see.

That is from an single system Verilog file I would like to get all the files that would be read while doing an normal compilations. 

One use case for this is to create make targets which depends on all the included files.

My idea is in to have an script and in that run

verible-verilog-syntax  --printtree --export_json    top.sv

And from that returned json tree recursively run the same command on all included files.

One problem is that we some times uses `ifdef to specify which files to include. I have not seen any way that I can specify defines to the   verible-verilog-syntax command. That is something like 
verible-verilog-syntax  --printtree --export_json  --define USE_COVERAGE  top.sv

An workaround would be to create an tmp systemverilog file where I first have my `define lines and then put the content from top.sv but that does not look to good.

I there an other better approach to get all the include files from an single  top.sv file? I only want the files list and nothing else.

[David Fang]

Yes, the verible-verilog-syntax tool itself knows nothing about multiple files.

However, you might be able to get this information more readily from 
verible-verilog-preprocessor preprocess ...

which attempts to preprocess a file (with some limitations at this time).

The verible-verilog-project file-deps tool might be of interest, which analyzes an entire project for dependencies between files via symbol references and resolution.  That is intended to discover relationships between files without any direct include-directive references, say a module is defined in one file, and referenced in others.  I'm not certain if this tool is integrated with preprocessing capabilities yet.

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