Macro replacement with verible-verilog-preprocessor

[Romain Ingrasciotta]

Hi,

I am trying to preprocess SystemVerilog code to replace Macros but there is some issues with the generated code.

Example verilog file with Macros:

 `define SVA_CLOCK clk

`define SVA_RESET reset

`define  MY_PROPERTY(NAME, PROPERTY, ERR_MSG="property failure.", DISABLE=`SVA_RESET, CLOCK=`SVA_CLOCK, SENSITIVITY=posedge) \
   `ifdef ASSERT_ON   \
usva_``NAME: assert property (     @(SENSITIVITY CLOCK) disable iff (DISABLE)       PROPERTY   ) ; \
 `endif

`define SIZE_OF_A 19

module foo(
 input logic clk,
 input logic reset,
 input [`SIZE_OF_A:0] logic a,
 input logic b,
 output logic z);

   `MY_PROPERTY(onehot, $onehot0({ a, b}), "not one hot")

endmodule : foo

./verible-v0.0-2678-g74f6bc9c/bin/verible-verilog-preprocessor preprocess foo.sv output :

// This is module foo.
`defineSVA_CLOCKclk
`defineSVA_RESETreset

`defineMY_PROPERTY(NAME,PROPERTY,ERR_MSG="property failure.",DISABLE=`SVA_RESET,CLOCK=`SVA_CLOCK,SENSITIVITY=posedge)\
   `ifdef ASSERT_ON   \
usva_``NAME: assert property (     @(SENSITIVITY CLOCK) disable iff (DISABLE)       PROPERTY   ) ; \
 `endif

`defineSIZE_OF_A19

module foo(
 input logic clk,
 input logic reset,
 input [19:0] logic a,
 input logic b,
 output logic z);

   \
`ifdefASSERT_ON\
usva_``onehot:assertproperty(@(posedgeclk)disableiff(reset)$onehot0({ a, b}));\
`endif

endmodule : foo

I see multiple issues here: 

• All Spaces inside macros have been removed
• The '\' are inserted in the macro replacement but it's only required for the multi-line macro definition and not for the preprocessed line of coded
• the "'``" while replacing NAME but it should not have been kept

Am I missing something or does the tool need enhancement to correclty preprocess this ?

Thanks in advance,

Romain