Language server UVM macro checking

[Boris Matveev (Borisus)]

Hello, verible community!

I'm new to Verible and linters at all, but this application is amazing!

I'm using VScode on my windows machine. I've installed verible extention with language server.

When I use UVM macros like `uvm_error, `uvm_fatal, etc, they're highlighted as syntax errors and no futher syntax errors are visible.

I've watched rules options, but still I can't figure out, how to stop checking macros. Is it even possible? 

Thank you.

[Henner Zeller]

On Fri, 9 Feb 2024 at 00:03, Boris Matveev (Borisus)
<mboris...@gmail.com> wrote:
>
> Hello, verible community!
>
> I'm new to Verible and linters at all, but this application is amazing!
> I'm using VScode on my windows machine. I've installed verible extention with language server.
>
> When I use UVM macros like `uvm_error, `uvm_fatal, etc, they're highlighted as syntax errors and no futher syntax errors are visible.

Verible is not working well with macros in all circumstances yet, so
this could be a contributing problem here.
Haven't looked at files with uvm macros recently, but usually they
should not harm parsing too much.

You can use the command line tool `verible-verilog-syntax` to parse
the file and see what errors it reports ( Get builds here
https://github.com/chipsalliance/verible/releases/latest ).

> I've watched rules options, but still I can't figure out, how to stop checking macros. Is it even possible?

Usually, while parsing, macros are often considered as behaving as
function calls, so that Verible does not have through all the macro
resolution as it might need to make parsing decisions in absense of
the available include files etc.
So there is currently no fine-control for that (I have that in the
works, but whatever time on weekend allows...).

So I'd say next step is to run verible-verilog-syntax on the file and
report back. Is the file you're looking at part of an OpenSource
Verilog project ? Then a link to that file would of course also be
useful.

Cheers,
Henner.

[Boris Matveev (Borisus)]

Hello, Henner! Thank you for your answer!

verible-verilog-syntax works correctly, but verible-verilog-lint doesn't. 

For example, if I create a syntax mistake in this code:

https://github.com/openhwgroup/core-v-verif/tree/master/cv32e40x/env/uvme/uvme_cv32e40x_cfg.sv

verible-verilog-syntax will show me exactly this error, but verible-verilog-lint will show me this message:

"49:4-26: preprocessing error at token "`uvm_object_utils_begin" : Error expanding macro identifier, might not be defined before."

And I guess that's why language server highlights only this macro, ignoring other mistakes.

пятница, 9 февраля 2024 г. в 11:18:04 UTC+3, h.zeller:

[Boris Matveev (Borisus)]

If I use verible-verilog-lint with  --parse_fatal=false  --lint_fatal=false, it shows me other style errors, but still shows only  "Error expanding macro..." instead my syntax error.

Best regards,

Boris.

пятница, 9 февраля 2024 г. в 11:18:04 UTC+3, h.zeller:

On Fri, 9 Feb 2024 at 00:03, Boris Matveev (Borisus)

[Sergey]

It is possible that the tool complains about undefined macros because of the "expand_macro" fall back? https://github.com/chipsalliance/verible/blob/07b310a3fd6a4a53dba24c96e99a89621c169cae/verilog/analysis/verilog_analyzer.cc#L229

Basically, the code has a verilog syntax error and the parser catch it and tries to expand macros as a fall back, but now it fails on an earlier undefined macro error. Should the fall back be other way around? I.e. start with expand_macro=true and fall back to no expand macro?