Config File

[Pratyush Jain]

Hi Verible Users

     I am trying to use this tool for the first time and want to set up the config file for the rules I want to follow for lint. I am able to install the tool and run it against a sv file using the command 

./verible-verilog-lint <filename.sv>

However, I want to set the rules like the naming convention i want to follow, if i want to turn off certain rules. Can someone point to an example of how such a file can be set up. I will highly appreciate any help I can get.

Thanks

Pratyush

[Tomasz Gorochowik]

Hi

Please take a look at the configuration section in the documentation: https://github.com/chipsalliance/verible/tree/master/verilog/tools/lint#rule-configuration

There is also a paragraph about the config files. Please let us know if you have any specific questions!

Best

Tom

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Tomasz Gorochowik
Antmicro Ltd | www.antmicro.com
Zwierzyniecka 3, 60-813 Poznan, Poland

[Pratyush Jain]

Hi Tom/Verible Users

    Thanks for the response, I was able to create a config file and remove rules, customize rules for things like line-length. I have a couple of other questions related to lint rules.

1) If i want to set a particular naming convention for signals as well as internal variables like bits, logic etc to say Camelcase or lower snake case.

    I tried signal-name-style=CamelCase/signal-name-style:CamelCase (or lower-snake-case), but it doesn't seem to work. Is there something I am missing here?

2) Is there any rule for indentation like 2 space indentation or a way to configure that. There is a no-tabs rule but I couldn't find anything related to indentation.

Thanks and Regards

Pratyush

[Mariusz Glebocki]

Hi,

1) If i want to set a particular naming convention for signals as well as internal variables like bits, logic etc to say Camelcase or lower snake case.

    I tried signal-name-style=CamelCase/signal-name-style:CamelCase (or lower-snake-case), but it doesn't seem to work. Is there something I am missing here?

"signal-name-style" is not configurable yet. It supports only snake_case.

https://chipsalliance.github.io/verible/lint.html#signal-name-style

 

2) Is there any rule for indentation like 2 space indentation or a way to configure that. There is a no-tabs rule but I couldn't find anything related to indentation.

There's not. However, you can try `verible-verilog-format` if you want consistent formatting.

[Pratyush Jain]

Thanks Mariusz for the response and Happy New Year everyone on this thread.

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