Preprocessing is a known area of development at this moment.
For example the linter and its syntax checker attempt to parse unpreprocessed forms (best-effort, without performing any expansion).
We do have some related tools in the works, for example a standalone preprocessor:
$ verible-verilog-preprocessor help preprocess
Inputs:
Accepts one or more Verilog or SystemVerilog source files to preprocess.
Each one of them will be prepropcessed independently which means that
declaration scopes will end by the end of each file, and won't be seen from
other files (so multiple files will _not_ be treated as compilation unit).
The +define+ and +include+ directives on the commandline are honored by
the preprocessor.
Output: (stdout)
The preprocessed files content (same contents with directives interpreted)
will be written to stdout, concatenated.
A little background: the linter was originally designed to plug into an interface that only sees one file at a time with zero additional context, nor access to related files, for simplicity.
In contrast, the verible-verilog-project tool was intended for operations that did have access to information across multiple files, which might seem more suitable for deeper analysis and true preprocessing.
Henner could probably explain better what the plans are around these tools.