Suppress Syntax issues and do regular formatting for sv files which has syntax issues!

[Sunil kumar Segu]

Hi,

It would be better to give a flag such that verible-verilog-format does only indentation but doesnot checks for syntax! The thing is sv/uvm files have some coding styles that might not present in LRM and accepted by simulators! So, as a formatter primary usecase could be do only indentation rather checking the syntax!

So, it woud be help full to quiet the syntax issues and do formatting for those files! How much ever possible.

Thanks,
Sunil.

[David Fang]

Acknowledged.  One limitation with the current formatter implementation is that it operates starting from a complete syntax tree (allowing for comments and directives).  To do what you suggest would require a significant re-design of the formatter to work based on lexical tokens without syntax.

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