Question: Can Verible Parser be used to extract netlists or other information for EDA purposes?

[MinJae Kim]

I really like your spirit:

The spirit of the project is that no-one should ever have to develop a SystemVerilog parser for their own application

but I don't know I can use this project for my other EDA project  (e.g. logic synthesis, RTL optimizer, etc). Is this suitable for their purpose?

Thank you very much for your project.