Verible Users

Hi everyone, I'm really enjoying using Verible with Neovim + Mason (Astronvim) for SystemVerilog

Acknowledged. One limitation with the current formatter implementation is that it operates starting

Hello again, It would be ideal to have a `prefix_regex` field for `generate-label-prefix`. The

This is for `verible-verilog-lint` in case that wasn't clear. On Tuesday, April 8, 2025 at 12:19:

Thanks a lot David. That worked. Extending the idea: we should also provide the pin names of standard

I am using below code with Verible. I can get file name, what about line number(s) for a given token/

Thanks for this wonderful parser + API. I am trying to use the Python API to write some simple lint

(replying again via reply all, sorry to David who will receive this twice) Hi David, Thanks for

Hi. If there are compiler directives in the System Verilog file, for example `pragma protect – then

Hi. Problem solved. Information about this should be added to the verible-verilog-lint documentation.

It is possible that the tool complains about undefined macros because of the "expand_macro"

I really like your spirit: The spirit of the project is that no-one should ever have to develop a

The obfuscator works as filter, so it takes the file from stdin So invoke it with file redirect

I response my self so there's information if someone else need this. After a conversation with

Usually, you`d use the `:install` feature as described in the install section https://github.com/

Yes, the verible-verilog-syntax tool itself knows nothing about multiple files. However, you might be

Preprocessing is a known area of development at this moment. For example the linter and its syntax

We haven't made this configurable yet. The place in the code the controls partition shaping

At the moment, formatting preserves vertical spacing. Some test cases can be found here: https://cs.

The formatter is far from perfect, so if you need to disable it over ranges of lines, use: ``` //

Thanks! On Wednesday, May 17, 2023 at 9:40:45 AM UTC-7 h.zeller wrote: > Can you help me confirm

Thanks David! On Tuesday, May 16, 2023 at 6:54:57 PM UTC-7 fan...@google.com wrote: At the moment,

> I am trying to try out the tool and have downloaded the Zipped windows 64 bit binary release.

We are now distributing also static binaries in the release section https://github.com/chipsalliance/

https://github.com/chipsalliance/verible/issues/1851 On Monday, April 3, 2023 at 8:26:09 PM UTC+2 fan

https://github.com/chipsalliance/verible/issues/1765 On Monday, April 3, 2023 at 8:21:42 PM UTC+2 fan

https://github.com/chipsalliance/verible/tree/master/verilog/tools/formatter#disabling-formatting-

Hi, I am trying to preprocess SystemVerilog code to replace Macros but there is some issues with the

Alternatively the user can add begin/end: if (something) begin do something end else begin do

Thanks very much! That does help quite a bit. I think I can use those scripts as a starting point.