Cooperation?

[Mark Christiaens]

I just wanted to thank you guys for this effort.  Writing a System Verilog grammar is a huge challenge!  (I know first hand: we at Sigasi develop an IDE for System Verilog (and VHDL)).  Our own System Verilog formatter is not great yet and we may be interested in cooperating on this front.  For example, we could help define formatting rules, improve the formatter implementation and create a test-set validating those formatting rules (and open source it all).  If the formatter is robust enough, we may integrate it in our product.  We regularly coach interns and this could be a good subject for such an internship.  Would Verible be open to such a cooperation?

Mark Christiaens

Head of Engineering @ Sigasi

[David Fang]

Hi Mark,

Nice to 'meet' you!  Thank you for approaching us with the offer to help with the Verible project.  I'd like to better understand your priorities to figure out where you can make the most impact.  It sounds like we all want a working formatter.  :)  I've also updated our github issue tracker with some Help Wanted topics.  I encourage you and your team to try out the tools, file issues, ask questions, and keep general discussion going.

David

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