Need guidance to add a lint feature

[Tushar Garg]

Hi Verible development team,

First of all, love your project, thank you for this.

I am trying to add a feature to Verible-lint, which checks that an "output" port in Verilog is always assigned and never read in the design. Is there a lint-rule already exist for this?

I am having a hard time navigating through all the project files and understanding the code. Is there a close enough example that you can point me to? I would request to add the feature once I am done coding using the example and have done testing.


Best,

Tushar

[Tomasz Gorochowik]

Hi Tushar

Thank you for taking interest in Verible! And sorry for the late reply.

Please take a look at the existing rules to look for inspiration: https://github.com/chipsalliance/verible/tree/master/verilog/analysis/checkers - these also generate a documentation with a summary of what's available: https://chipsalliance.github.io/verible/lint.html

The best way to start would be to use the syntax checker tool: https://github.com/chipsalliance/verible/tree/master/verilog/tools/syntax with the --printree argument. All the checking the linter rules do is based on the syntax tree so it's best to identify what you're looking for first, and then start playing with the implementation (based on one of the rules from the first link I pasted).

You can also file a github issue if you find some particular problems.

Thanks!

Tom

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Tomasz Gorochowik
Antmicro Ltd | www.antmicro.com
Zwierzyniecka 3, 60-813 Poznan, Poland