Cascading Shift Registers

[Michael Kessler]

So I'm just now getting into shift registers with a word clock that I'm building.

I can kind of understand how the shift registers are working (kind of) but I don't exactly see how the cascading shift register works.

For instance:

Arduino => shift register ic => shift register ic

Of the three pins, all are tied together except data, where data is, on the first ic tied to the arduino, and the 2nd is on a pin of the first ic.


Does anyone know of a good page to describe how the 2nd chip is being set?  It seems odd to me because it feels like it would be missing lots of clock cycles and therefore putting either lots of 1's or 0's based on the current state of that output pin.

Do shift register ICs have special logic for when they are hooked up to each other or is it just a clever usage of them that works because of their inherent properties?

-Kessler

[Tom Keddie]

Michael,

Without a circuit diagram I can't be sure of what you're describing but
I think I know. A nickname for this is a bucket brigade, the data
entering the first chip is clocked through all the flip flops in that
chip. The data input of the next chip is connected to the output of the
last flip flop in the previous chip. This mimics the internal diagram
of each chip so both will behave as a continuous chain (until your clock
gets really fast).

http://en.wikipedia.org/wiki/File:4-Bit_SIPO_Shift_Register.png

Does that help?

Tom

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[Graeme Smecher]

Hi Michael,

Is there a schematic available? What part are you using?

I've attached a schematic from a board I use. It's got two 74HVC595
shift-registers cascaded, to form a really crude SPI expander; you
should probably ignore all but the shift-register interconnections.
These shift registers have two clocks (SCK and RCK); one shuffles data
through the shift register, and the other latches the current state on
the QA-QH outputs.

In this case, the Q'H output on the first shift register feeds the data
input on the second. It's pretty much designed to cascade registers this
way. The separated clocks allow data to be shuffled behind the scenes,
without affecting circuitry attached to the outputs. I'm guessing parts
are probably similar, since it seems like an obviously useful building
block.

best,
Graeme

[Loial Otter]

If you wire the highest bit from one into the input of the second and clock at the same time, the highest bit shouldn't have changed by the time the clock tells it to read (there are special outputs on some chips that change delayed). Large numbers of chips in a row require a power driver on the clock line due to the current to drive it. I've found this to be the case when there's more than even 6 LS series chips and more than 20 HC or other higher input impedance chips.

[Dave Hylands]

Hi Michael,

On Tue, Nov 27, 2012 at 10:05 AM, Michael Kessler <mike...@gmail.com> wrote:

It's really just how they work.

Here's a data sheet for a 74HC595: http://www.nxp.com/documents/data_sheet/74HC_HCT595.pdf

If you look at Figure 4 on page 3 it shows how the 8-bits are arranged internally within the chip, and it should be obvious from that picture that if you put another shift register beside this and connect Q7S to DS that you're really just creating a 16-bit shift-register.

I think that it also imporant to understand the difference between the shift portions of the register (the upper D-FlipFlop in that figure) versus the storage portion (the lower D-FlipFlop)

The real secret to understanding the cascading registers is that Q7S comes from the "shift" portion and Q7 comes from the "storage" portion.  So when the clock is shifting bits, Q7S will be changing and won't be in a steady state like Q7 is.
 

--
Dave Hylands
Shuswap, BC, Canada
http://www.davehylands.com