[riscv] Add simulator support for 256/512 bit vectors. [v8/v8 : main]
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Kasper Lund (Gerrit)
Sep 25, 2025, 9:57:52 AM (2 days ago) Sep 25
to Florian Loitsch, v8-re...@googlegroups.com
Attention needed from Florian Loitsch
Kasper Lund voted and added 2 comments![]( "Open in Gerrit")
Votes added by Kasper Lund
| Code-Review | +1 |
2 comments
File src/codegen/riscv/base-constants-riscv.h
Line 346, Patchset 1 (Latest):
static_assert(kSimulatorRvvVLEN <= kMaxRvvVLEN, "RvvVLEN size unimplemented");Kasper Lund . resolved
```suggestion
static_assert(kSimulatorRvvVLEN <= kMaxRvvVLEN, "RvvVLEN size is unimplemented");
```
File src/execution/riscv/simulator-riscv.cc
Line 1860, Patchset 1 (Latest):
PrintF("%016" PRIx64, value.chunks[i]);Kasper Lund . resolved
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Florian Loitsch (Gerrit)
Sep 26, 2025, 4:35:31 AM (yesterday) Sep 26
to V8 LUCI CQ, Kasper Lund, v8-re...@googlegroups.com
Florian Loitsch added 2 comments![]( "Open in Gerrit")
File src/codegen/riscv/base-constants-riscv.h
Line 346, Patchset 1:
static_assert(kSimulatorRvvVLEN <= kMaxRvvVLEN, "RvvVLEN size unimplemented");Kasper Lund . resolved
```suggestion
static_assert(kSimulatorRvvVLEN <= kMaxRvvVLEN, "RvvVLEN size is unimplemented");
```
Florian Loitsch
done.
File src/execution/riscv/simulator-riscv.cc
Line 1860, Patchset 1:
PrintF("%016" PRIx64, value.chunks[i]);Kasper Lund . resolved
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Florian Loitsch (Gerrit)
Sep 26, 2025, 5:32:58 AM (yesterday) Sep 26
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Florian Loitsch voted Commit-Queue+2![]( "Open in Gerrit")
| Commit-Queue | +2 |
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V8 LUCI CQ (Gerrit)
Sep 26, 2025, 5:35:13 AM (yesterday) Sep 26
to Florian Loitsch, Kasper Lund, v8-re...@googlegroups.com
V8 LUCI CQ submitted the change with unreviewed changes![]( "Open in Gerrit")
Unreviewed changes
1 is the latest approved patch-set.
The change was submitted with unreviewed changes in the following files:
```
The name of the file: src/codegen/riscv/base-constants-riscv.h
Insertions: 2, Deletions: 1.
@@ -343,7 +343,8 @@
static_assert(kSimulatorRvvVLEN >= 128, "RvvVLEN must be >= 128 bit");
static_assert((kSimulatorRvvVLEN & (kSimulatorRvvVLEN - 1)) == 0,
"RvvVLEN must be a power of 2");
-static_assert(kSimulatorRvvVLEN <= kMaxRvvVLEN, "RvvVLEN size unimplemented");
+static_assert(kSimulatorRvvVLEN <= kMaxRvvVLEN,
+ "RvvVLEN size is unimplemented");
#else
constexpr int kSimulatorRvvVLEN = 128;
#endif
```
```
The name of the file: src/execution/riscv/simulator-riscv.cc
Insertions: 4, Deletions: 1.
@@ -1857,7 +1857,10 @@
VRegisterValue value = GetVRegisterValue(vregnum);
PrintF("\t%s:0x", VRegisters::Name(vregnum));
for (int i = VRegisterValue::kChunks - 1; i >= 0; i--) {
- PrintF("%016" PRIx64, value.chunks[i]);
+ const char* format = i != VRegisterValue::kChunks - 1
+ ? "_%016" PRIx64
+ : "%016" PRIx64;
+ PrintF(format, value.chunks[i]);
}
PrintF("\n");
#endif
```
Change information
Commit message:
[riscv] Add simulator support for 256/512 bit vectors.
The default vector size of the simulator is 128 bits, but can be changed
by changing the gn arg 'riscv_rvv_vlen'.
Change-Id: I4d8152eb1c12bba35bc341281a84e17ef310014a
Reviewed-by: Kasper Lund <kas...@rivosinc.com>
Commit-Queue: Florian Loitsch <floi...@rivosinc.com>
Cr-Commit-Position: refs/heads/main@{#102782}
Files:
- M src/codegen/riscv/base-constants-riscv.h
- M src/execution/riscv/simulator-riscv.cc
- M src/execution/riscv/simulator-riscv.h
Change size: M
Delta: 3 files changed, 70 insertions(+), 51 deletions(-)
Branch: refs/heads/main
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Code-Review: +1 by Kasper Lund
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