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📍 Job mac-m1_mini_2020-perf/speedometer3 complete.
See results at: https://pinpoint-dot-chromeperf.appspot.com/job/124bab21510000
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Code-Review | +1 |
lgtm
The bots may show a possible regression though; maybe we need to revert this. It's unclear to me where that would come frome given on the ABI this should be better or the same as before. The CAS loop also has a filtering bailout.
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lgtm
The bots may show a possible regression though; maybe we need to revert this. It's unclear to me where that would come frome given on the ABI this should be better or the same as before. The CAS loop also has a filtering bailout.
Are the bots tested with PGO? I'm not sure if there will be less functions inlined if we made a change like this. It seems to be less likely that an actual data race will happen during the CAS, so I'm not sure whether the filtering bailout works many times.
For x64, the assembly behind FetchOr should be a single atomic bitwise or instruction with a LOCK prefix. I'm not a arm expert but it seems that they have a similar `LDSET` instruction as well. Maybe we can consider making this architecture dependent if it does incur regression on arm? (seems that win-11 bots have some improvement)
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Hao A Xulgtm
The bots may show a possible regression though; maybe we need to revert this. It's unclear to me where that would come frome given on the ABI this should be better or the same as before. The CAS loop also has a filtering bailout.
Are the bots tested with PGO? I'm not sure if there will be less functions inlined if we made a change like this. It seems to be less likely that an actual data race will happen during the CAS, so I'm not sure whether the filtering bailout works many times.
For x64, the assembly behind FetchOr should be a single atomic bitwise or instruction with a LOCK prefix. I'm not a arm expert but it seems that they have a similar `LDSET` instruction as well. Maybe we can consider making this architecture dependent if it does incur regression on arm? (seems that win-11 bots have some improvement)
Yeah, I think it's just okay to land and try and let PGO pick it up.
Really, from what I understand this should always be better or the same.
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Hao A Xulgtm
The bots may show a possible regression though; maybe we need to revert this. It's unclear to me where that would come frome given on the ABI this should be better or the same as before. The CAS loop also has a filtering bailout.
Michael LippautzAre the bots tested with PGO? I'm not sure if there will be less functions inlined if we made a change like this. It seems to be less likely that an actual data race will happen during the CAS, so I'm not sure whether the filtering bailout works many times.
For x64, the assembly behind FetchOr should be a single atomic bitwise or instruction with a LOCK prefix. I'm not a arm expert but it seems that they have a similar `LDSET` instruction as well. Maybe we can consider making this architecture dependent if it does incur regression on arm? (seems that win-11 bots have some improvement)
Yeah, I think it's just okay to land and try and let PGO pick it up.
Really, from what I understand this should always be better or the same.
Thanks, I will land this CL.
I think in theory this should always be better or the same as well, I'm just saying that making it architecture dependent can give us some time to investigate where the regression on arm comes from.
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Introduce Relaxed_FetchOr for MarkBit::Set
Relaxed_SetBits were using Relaxed_CompareAndSwap to set the bits. It
contains a loop to ensure that the three operations (getting bits
/bitwise or/setting bits) are atomic. However, when all the bits to be
set are 1, we can use atomic fetch_or directly to avoid this loop.
This can be used in MarkBit::Set.
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