[riscv] Support fractional LMUL check in simulator [v8/v8 : main]

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Yahan Lu (LuYahan) (Gerrit)

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Jan 30, 2026, 2:14:01 AM (5 days ago) Jan 30
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Yahan Lu (LuYahan) voted Commit-Queue+1

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Yahan Lu (LuYahan) (Gerrit)

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Jan 30, 2026, 2:14:26 AM (5 days ago) Jan 30
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Yahan Lu (LuYahan) voted and added 1 comment

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File-level comment, Patchset 2 (Latest):
Yahan Lu (LuYahan) . resolved

LGTM.
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Ji Qiu (Gerrit)

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Feb 3, 2026, 7:58:26 AM (20 hours ago) Feb 3
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Ji Qiu added 3 comments

File src/execution/riscv/simulator-riscv.h
Line 1003, Patchset 7 (Latest): inline void set_rvv_vill(bool trace = true) { vtype_ |= (0x1ULL << 63); }
Ji Qiu . unresolved

It's better to distinguish between RV32 and RV64 since RV32 is still in the tree: the vill bit is at bit 63 only on RV64, and macros can be used to separate these two cases.

File src/execution/riscv/simulator-riscv.cc
Line 8376, Patchset 7 (Latest): set_rvv_vill();
Ji Qiu . unresolved

According to https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#611-unsupported-vtype-values, "then the (1)vill bit is set in vtype, (2)the remaining bits in vtype are set to zero, and (3)the vl register is also set to zero." It's seems step (2) is missing here?

Line 8410, Patchset 7 (Latest): set_rvv_vill();
Ji Qiu . unresolved

Same comment as above.

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    Zhijin Zeng (Gerrit)

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    12:53 AM (3 hours ago) 12:53 AM
    to Yahan Lu (LuYahan), V8 LUCI CQ, Ji Qiu, Kasper Lund, Florian Loitsch, v8-re...@googlegroups.com, v8-risc...@chromium.org
    Attention needed from Florian Loitsch, Ji Qiu, Kasper Lund and Yahan Lu (LuYahan)

    Zhijin Zeng added 3 comments

    File src/execution/riscv/simulator-riscv.h
    Line 1003, Patchset 7: inline void set_rvv_vill(bool trace = true) { vtype_ |= (0x1ULL << 63); }
    Ji Qiu . unresolved

    It's better to distinguish between RV32 and RV64 since RV32 is still in the tree: the vill bit is at bit 63 only on RV64, and macros can be used to separate these two cases.

    Zhijin Zeng

    Done.

    File src/execution/riscv/simulator-riscv.cc
    Line 8376, Patchset 7: set_rvv_vill();
    Ji Qiu . unresolved

    According to https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#611-unsupported-vtype-values, "then the (1)vill bit is set in vtype, (2)the remaining bits in vtype are set to zero, and (3)the vl register is also set to zero." It's seems step (2) is missing here?

    Zhijin Zeng

    Done.

    Line 8410, Patchset 7: set_rvv_vill();
    Ji Qiu . resolved

    Same comment as above.

    Zhijin Zeng

    Done

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