[maglev] Handle equal inputs in Float64Max/Min [v8/v8 : main]

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Victor Gomes (Gerrit)

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Feb 23, 2026, 9:10:41 AM (24 hours ago) Feb 23
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Marja Hölttä (Gerrit)

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Feb 23, 2026, 9:12:27 AM (24 hours ago) Feb 23
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V8 LUCI CQ (Gerrit)

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Change information

Commit message:
[maglev] Handle equal inputs in Float64Max/Min

A DCHECK failure left != right in macro-assembler-arm.cc was triggered
because the compiler was emitting Float64Max (or Min) nodes where both
inputs were the same register.

While Maglev generally avoids emitting these nodes if the inputs are
known to be equal, this case can still occur after unwrapping conversion
nodes during the phi untagging phase.
Fixed: 486530209
Change-Id: I07f2a3b883a1b2a604aace8add5201041d0fc0e1
Auto-Submit: Victor Gomes <victo...@chromium.org>
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Reviewed-by: Marja Hölttä <ma...@chromium.org>
Cr-Commit-Position: refs/heads/main@{#105374}
Files:
  • M src/maglev/arm/maglev-ir-arm.cc
  • M src/maglev/arm64/maglev-ir-arm64.cc
  • M src/maglev/x64/maglev-ir-x64.cc
  • A test/mjsunit/maglev/regress-486530209.js
Change size: M
Delta: 4 files changed, 76 insertions(+), 4 deletions(-)
Branch: refs/heads/main
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Yahan Lu (LuYahan) (Gerrit)

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Feb 23, 2026, 9:07:46 PM (12 hours ago) Feb 23
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Yahan Lu (LuYahan) has uploaded the change for review

Commit message

[riscv][maglev] Handle equal inputs in Float64Max/Min

Port commit 020934e177a8ffae9c978bbbfe8690e2697360f2
Change-Id: I5dd2ae434c62f408d3dfb14c73c84b3845a223ce

Change diff

diff --git a/src/maglev/riscv/maglev-ir-riscv.cc b/src/maglev/riscv/maglev-ir-riscv.cc
index aabd02b..3d5438f 100644
--- a/src/maglev/riscv/maglev-ir-riscv.cc
+++ b/src/maglev/riscv/maglev-ir-riscv.cc
@@ -873,10 +873,19 @@
 void Float64Min::SetValueLocationConstraints() {
   UseRegister(LeftInput());
   UseRegister(RightInput());
-  DefineAsRegister(this);
+  if (LeftInput().node() == RightInput().node()) {
+    DefineSameAsFirst(this);
+  } else {
+    DefineAsRegister(this);
+  }
 }
 void Float64Min::GenerateCode(MaglevAssembler* masm,
                               const ProcessingState& state) {
+  if (LeftInput().node() == RightInput().node()) {
+    DCHECK_EQ(ToDoubleRegister(result()), ToDoubleRegister(LeftInput()));
+    return;
+  }
+
   DoubleRegister left = ToDoubleRegister(LeftInput());
   DoubleRegister right = ToDoubleRegister(RightInput());
   DoubleRegister out = ToDoubleRegister(result());
@@ -887,11 +896,19 @@
 void Float64Max::SetValueLocationConstraints() {
   UseRegister(LeftInput());
   UseRegister(RightInput());
-  DefineAsRegister(this);
+  if (LeftInput().node() == RightInput().node()) {
+    DefineSameAsFirst(this);
+  } else {
+    DefineAsRegister(this);
+  }
 }
 
 void Float64Max::GenerateCode(MaglevAssembler* masm,
                               const ProcessingState& state) {
+  if (LeftInput().node() == RightInput().node()) {
+    DCHECK_EQ(ToDoubleRegister(result()), ToDoubleRegister(LeftInput()));
+    return;
+  }
   DoubleRegister left = ToDoubleRegister(LeftInput());
   DoubleRegister right = ToDoubleRegister(RightInput());
   DoubleRegister out = ToDoubleRegister(result());

Change information

Files:
  • M src/maglev/riscv/maglev-ir-riscv.cc
Change size: S
Delta: 1 file changed, 19 insertions(+), 2 deletions(-)
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Yahan Lu (LuYahan) (Gerrit)

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Feb 23, 2026, 9:08:45 PM (12 hours ago) Feb 23
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Ji Qiu (Gerrit)

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V8 LUCI CQ (Gerrit)

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V8 LUCI CQ submitted the change

Change information

Commit message:
[riscv][maglev] Handle equal inputs in Float64Max/Min

Port commit 020934e177a8ffae9c978bbbfe8690e2697360f2
Bug: 486530209
Change-Id: I5dd2ae434c62f408d3dfb14c73c84b3845a223ce
Reviewed-by: Ji Qiu <qi...@iscas.ac.cn>
Commit-Queue: Ji Qiu <qi...@iscas.ac.cn>
Auto-Submit: Yahan Lu (LuYahan) <ya...@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#105395}
Files:
  • M src/maglev/riscv/maglev-ir-riscv.cc
Change size: S
Delta: 1 file changed, 19 insertions(+), 2 deletions(-)
Branch: refs/heads/main
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 Gerrit-Project: v8/v8 


 Gerrit-Branch: main 


 Gerrit-Change-Id: I5dd2ae434c62f408d3dfb14c73c84b3845a223ce 


 Gerrit-Change-Number: 7599842 


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 Gerrit-Owner: Yahan Lu (LuYahan) <ya...@iscas.ac.cn> 


 Gerrit-Reviewer: Ji Qiu <qi...@iscas.ac.cn> 


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