Lab 1
D Lee
The following is valuable information located on the ece223 course disk
under '/docs/lab1info.txt' .
Remember that the lab period is only for demonstration purposes - do all
design and speedwiring beforehand.
Dora.
======================
98/01/28
STEPS TO DESIGN LAB 1
1. Division of Work
Lab 1 has two parts to it so each partner should design one part to
begin with. Be careful in choosing your signal names. For ease
of testing by the TAs you MUST use the label names shown below.
This will allow us to test your simulated design with a simulation
command file.
2. Where to Start
Begin with a truth table of inputs and outputs. From your truth table
you can use Karnaugh maps to simplify the expressions for each of the
outputs. ONLY USE BASIC GATES eg. AND, NAND, OR, NOR, XOR, NOT.
(Note, in Workview specify thes by their 74LSxxx TTL part number). The
parts kit that you were given during lab 0 should have most of the
chips you will need. If you need a chip that is not in the set,
sign it out from your Technologist at the begining lab. On the
ECE223@electrical disk is a file SEMICON.LST which lists the chips
available. You will need a TTL data book to read the
pinouts (pin positions) for each of the chips you use. If you don't
have a TTL data book, there is one in the reference section of the DC
library. Also, the Workview software will show you the pin numbers.
Each speedwire can hold 14 basic (16 pins or less) TTL chips
so you must design Parts I and II to use at most 14 chips. It makes
sense to look at the chips available to you in your chip set before
you start simplifying. Try and use all of the gates in a chip (eg.
try and use all four gates in a QUAD two input AND 74LS08). This will
help you to reduce the number of chips needed.
3. Schematic Entry
I suggest entering both Parts I and II on separate schematics. If you
choose to put both circuits on the same schematici, be very
careful not to use duplicate label names by mistake. Using label names
can drastically reduce the net wiring on your schematic. You must use
the standard TTL component library. For example, if you want a
two input AND gate in Workview you do ADD -> COMPONENT and type 74LS08.
It will bring up a two input AND gate and even include the pin numbers as
they correspond to the actual chip. This will really help when you
start speedwiring.
Please use these labels on your schematics and simulations:
Part I Inputs R1, R0, X1, Y1, Z1
Outputs D1, D0, A
Part II Inputs W2, X2, Y2, Z2
Outputs A2, B2, C2, D2, E2, F2, G2
4. Simulation
I suggest that you use one .cmd for each part when simulating using VIEWSIM.
You can use the simulation commands from Lab 0 as a guideline when you
design your own .cmd file. Two very useful simulation commands are CHECK
and WATCH. Also, read the DEBUGGING section in the lab manual. MAKE SURE
YOUR SIMULATION IS CORRECT BEFORE YOU EVEN THINK OF SPEEDWIRING.
5. Speedwiring
Read the two pages that immediately follow the description of Lab 1 in the
lab manual (pp Lab1-3 Lab1-4). Use your Workview schematic when speedwiring
because it will have the pin numbers right on it. Be very careful! It's very
easy to make mistakes because you speedwire from the bottom of the board so
you are looking at a MIRROR IMAGE of the chips. All inputs and outputs will go
through ribbon cables P1 and P2. In general, the inputs go to toggle
switches on the test chassis and the outputs go to LEDs. There is a
page (Tcp-1) towards the end of the lab manual that describes this.
DON'T PUT THE CHIPS IN THE BOARD UNTIL YOU HAVE VERIFIED THAT THERE IS NO SHORT
CIRCUIT BETWEEN VCC AND GROUND. This means that you will wire up the board
before the lab and put the chips in during the lab.
Here are some suggestions for your input/output connections on the speedwire:
Part 1
Connect your 5 inputs (R1, R0, X1, Y1, Z1) to pins 1, 2, 3, 4, 5 on
ribbon cable P1. These are the first 5 toggle switches on the test
chassis.
Connect your three outputs (D1, D0, A) to pins 17, 18, 19 on ribbon
cable P1. These are the first three LEDs on the test chasis.
Part 2
Connect your four inputs (W2, X2, Y2, Z2) to pins 9, 10, 11, 12 on
ribbon cable P1. These are the four push button switches.
You could also re-use the toggles from part 1, using pins 1, 2, 3 and 4.
Connect your seven outputs (A2, B2, C2, D2, E2, F2, G2) to pins
13, 14, 15, 16, 17, 18, 19 on ribbon cable P2. These are connected
to the right hand seven segment display.
Page Swp 1 in the Lab Manual shows how ribbon cables P1 and P2 are
connected to the speedwire board and and the pin numbering for each
cable.
MARKING SCHEME
Total Marks: 50
Part I II
Simulation Demo 10 10
Hardware Demo 10 10
Write Up 5 5
-- --
25 25
Simulation Demo
During the actual lab period the first thing you will do is bring up your
schematic in Workview. The TA will ask you to run your .cmd files for both
parts in Viewsim and he will run some .cmd files that he has prepared to
verify whether your simulated design is correct. Once your design is
verified, you can then go to the hardware lab where you will first check
for a short circuit between VCC and ground. If there is no short circuit,
you can place the chips in the board.
Hardware Demo
In the hardware lab you will test and debug your board using the test
chassis and logic probe. You may need to correct some wiring mistakes.
Once you feel that your hardware circuit is working correctly, you can
demo it to the TA.
Write Up (BE BRIEF)
It should include:
-Truth tables (for both parts)
-Karnaugh maps (if you used them) (for both parts)
-Printout of your schematics
-List of TTL chips you used
-Printout of your .cmd files
-Description of any problems encountered during schematic capture and
simulation (eg. duplicate label names)
-Short description of hardware debugging and testing
HAND IN ONE REPORT PER GROUP. REPORTS ARE DUE 24 HOURS AFTER THE END OFr
THE LAB PERIOD!
I know that's a lot to absorb but we want to be very clear on what we
expect of you. If you have any questions (especially if you are unsure
about what the lab description is asking of you eg. in part I the
function of the Alarm signal is a little difficult to understand) don't
hesitate to ask, just post to the newsgroup.
------------------------------------------------------------------------------
Dora Lee
dh...@ece.uwaterloo.ca
M Krzeminski
Question #1: What is the average number of Gates used in this lab?
We have 23 in part I and 21 in part II not including the inverters. Is
this to many?
Dora Lee
In article <34D611...@novice.uwaterloo.ca>,
The board can only fit 14 IC's -- so if you can fit 44 gates into the 14
IC's there is no problem.
Dora.
--
------------------------------------------------------------------------------
Dora Lee
dh...@ece.uwaterloo.ca
------------------------------------------------------------------------------
Melanie Barker
: ONLY USE BASIC GATES eg. AND, NAND, OR, NOR, XOR, NOT.
Does this mean XNOR is not considered a "basic gate", or was it just
forgotten in this list?
--
******************************************************************************
Melanie Barker
3A Computer Science w/Electrical Engineering Electives
University of Waterloo
maba...@undergrad.math.uwaterloo.ca
******************************************************************************
Eric Praetzel
In article <Enry4...@undergrad.math.uwaterloo.ca> maba...@cayley.uwaterloo.ca (Melanie Barker) writes:
>: ONLY USE BASIC GATES eg. AND, NAND, OR, NOR, XOR, NOT.
>Does this mean XNOR is not considered a "basic gate", or was it just
>forgotten in this list?
Looking at the back of the lab manual you'll see a list of ICs which we
try to keep in stock.
As I posted earlier, the 7486 is a very commonly used chip; and it is
also in that list of ICs. But, it is an XOR; not XNOR.
Eric Praetzel, http://ece.uwaterloo.ca/~praetzel http://sca.uwaterloo.ca
Microsoft is NOT the answer. Microsoft is the Question. The answer is: "NO!"