Exam

[Leon Zheng]

I am wondering if someone could tell me what back-annotation means.

Leon Zheng

[Weebs]

Nobody knows, Leon..... Nobody really knows...

Weber

[Lpadrpadba Clkopad]

"Back-annotation is the process of taking gate and wiring delay information
from the placed and routed layout and attatching it to the original netlist
so it can be used for timing simulation."
-From the 223 Final '95 Solutions, question 10(b)(1)

It's funny you asked that, actually... I was doing a little circuit design
myself last week (a personal project), a new controller circuit for my
motorized programmable electronic speedwiring pen. I needed it to recognize
the new shapes of the 76xxGS series of IC's. In my fundamental mode design
I had a possible essential hazard... so I just whipped up a little prototype
(using one of my many non-electronic WTF speedwiting pens, still available
for $9.99 each), and back-annotated. Wouldn't you know it, the hazard
wasn't a problem, so additional delay elements weren't necessary. Phew!

Hope that helped for the exam...

Lpadrpadba Clkopad

Leon Zheng wrote in message <353A64...@engmail.uwaterloo.ca>...