Lab#3

[Muhammad M. Khellah]

Some students are still confused on how to design the
control block. The most important thing that you should
keep in mind is that you are asked to design a SYNCHRONOUS
digital circuit. This means that your control block should
by synchronous. In other words, you have to have a CLOCK signal
in your control block to decide when you should/shouldn't
move from one state to another.

I explained in the tutorials how you can design the control block.
Start from the STATE DIAGRAM then STATE TABLE then write equations
for the [control block outputs] and [FF excitation inputs] in terms of
the [present states] and the [control block inputs].

I gave you some example of what inputs you need to include as your
control block inputs. You have to decide on the rest of these
inputs and whether you should assign 0,1,X to these inputs at any
entry..

-- M. M. Khellah

[Muhammad Khellah]

Tomorrow Friday March 27, 1998 will be the last day to check off
groups for lab#3. So students already signed up for tomorrow, please
try to demo your lab to one of the TAs (You had 2 weeks to prepare
for this lab and so no extra time will be given). Also the following
groups didn't sign up and they SHOULD appear tomorrow if they want
a mark for lab#3 (that is if they want to pass the course :)
G#31 (Chan and Zhu)
G#45 (Lewis and Shaw)
G#95 (Iu)

and

Chu, Steven
Hirani, Hussein
Hwang, Tzu

--
-- M. M. Khellah

+---------------------------------------------------------------------------+

[Jim Field]

In article <89094696...@globe.uwaterloo.ca>,

Muhammad Khellah <khe...@vlsi.uwaterloo.ca> wrote:
>for this lab and so no extra time will be given). Also the following
>groups didn't sign up and they SHOULD appear tomorrow if they want
>a mark for lab#3 (that is if they want to pass the course :)

Actually I think I indicated at the start of the term that
if you didn't do the lab you got zero for it. So not
doing the lab doesn't cause you to fail the course automatically -
but it does make it more likely.

J Field