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Project Task 3a: pipelined or simply staged?
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z2long
Mar 21, 2012, 12:35:22 PM3/21/12
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Task 3a asks us to break the implementation of Task 1 into stages, which
is also reflected in w450.v starting point. Does this also require the
processor design in Task 3a be pipelined?
I ask because I feel the instructions given in w450.v isn't sufficient for
a pipelined design for at least that each stage will not be able to
execute in paralle. Or am I wrong?
is also reflected in w450.v starting point. Does this also require the
processor design in Task 3a be pipelined?
I ask because I feel the instructions given in w450.v isn't sufficient for
a pipelined design for at least that each stage will not be able to
execute in paralle. Or am I wrong?
SPk
Mar 24, 2012, 12:02:05 AM3/24/12
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On Mar 21, 12:35 pm, z2long <z2l...@linux032.student.cs.uwaterloo.ca>
wrote:
> I ask because I feel the instructions given in w450.v isn't sufficient for
> a pipelined design for at least that each stage will not be able to
> execute in paralle. Or am I wrong?
by "instructions given in w450.v" do you mean, stages provided in the
sample code? You'll have to define the stages (possibly add more) and
pipeline them by handling the hazards.
wrote:
> Task 3a asks us to break the implementation of Task 1 into stages, which
> is also reflected in w450.v starting point. Does this also require the
> processor design in Task 3a be pipelined?
>
It has to be pipelined.
> is also reflected in w450.v starting point. Does this also require the
> processor design in Task 3a be pipelined?
>
> I ask because I feel the instructions given in w450.v isn't sufficient for
> a pipelined design for at least that each stage will not be able to
> execute in paralle. Or am I wrong?
sample code? You'll have to define the stages (possibly add more) and
pipeline them by handling the hazards.
Vasily Suslov
Mar 30, 2012, 4:31:25 PM3/30/12
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stages provided in the sample code, IF and ID?
suk...@gmail.com
Apr 1, 2012, 9:58:59 PM4/1/12
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On Friday, March 30, 2012 4:31:25 PM UTC-4, Vasily Suslov wrote:
> Does this mean that our implementation in Task 1 should only have two
> stages provided in the sample code, IF and ID?
Task 1 doesn't require that you divide it into stages. But you are free to use more stages if you want to.
> Does this mean that our implementation in Task 1 should only have two
> stages provided in the sample code, IF and ID?
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