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Task 3 marking
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dji
Mar 30, 2012, 10:56:32 PM3/30/12
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How will task 3 be marked? I understand that we have to get the pipeline version correct, and working, but is there a implied requirement on performance or throughput improvement? My implementation for Task 1 already finishes 1 instruction every 2 cycles, and it is kind of hard to improve on that, given that there aren't that many architected registers.
suk...@gmail.com
Apr 1, 2012, 10:00:55 PM4/1/12
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On Friday, March 30, 2012 10:56:32 PM UTC-4, dji wrote:
> How will task 3 be marked? I understand that we have to get the pipeline version correct, and working, but is there a implied requirement on performance or throughput improvement? My implementation for Task 1 already finishes 1 instruction every 2 cycles, and it is kind of hard to improve on that, given that there aren't that many architected registers.
You just have to get a correct implementation. Performance enhancement is not a requirement.
> How will task 3 be marked? I understand that we have to get the pipeline version correct, and working, but is there a implied requirement on performance or throughput improvement? My implementation for Task 1 already finishes 1 instruction every 2 cycles, and it is kind of hard to improve on that, given that there aren't that many architected registers.
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