Lab 4 Description

[Keith Ribe]

David, or anyone else who has started, what should be included in a
good description of the memory system for Lab 4. I have all the
information needed, I just am not sure what is important and essential
to include to explain the memory mountain. Any help would be greatly
appreciated.

Keith

[David L. Rager]

This answer will come to me over time, but here are three ideas:

-- Determine the stride size of your processor and explain why you
came to that conclusion
-- Determine the sizes of the different levels of cache and explain
why you came to that conclusion
-- Find information on the processor, e.g., the minimum transistor
process size (65nm vs 90nm vs 130nm), what year it came out, a link to
a reference sheet from Intel or AMD.

I want to emphasize the "concise and clear" part of the lab. If you
say the same thing redundantly, points will be deducted. Find
something new and meaningful to say.

[mdm...@cs.utexas.edu]

David-

Can you elaborate on what you mean by the processor's stride size? I'm familiar with the term in the context of how far apart sequentially accessed elements are in memory, but I don't know what you mean when you say that the processor has a specific stride size.

Would that be the width of the lines in the cache?

Thanks.

[David L. Rager]

"Stride size" describes the code, not the processor. You have to look
at the code to figure out what it means.

As you hint at near the end of your question, I think stride size
helps determine the width of a cache line.

[Daniel Kuang]

From the looks of it, it won't be easy to write one page with useful
and relevant information, let alone two.

So, aside from the max. limit, is there a minimum?

[David Rager]

I've found the source of some confusion. The first bullet in this
message implies that processors have a stride size. That was
incorrect. I probably could have inserted the word "optimal" before
the word "processor" and it would read correctly. The performance of
the different stride sizes should allow you to deduce the cache's line
size. That being said, I have yet to see a graph that clearly shows
me the line size, so such deduction is probably still just an
estimate.

If you're still confused about what the stride size is, you probably
need to study the source code for lab 4 more. A stride of 1 means it
reads all of the elements. A stride of 2 means it skips every other
element. A stride size of 3 means the code skips 2 elements for every
one element it reads.

[John Barry]

David, should we include the raw data in our writeup?

- John

[David L. Rager]

I won't be looking for it specifically, but if you want to include it
in an appendix, I don't see the harm. If your graph looks weird, I
might look for it.