Lab 4 Question

[Mhuff]

After graphing my data, it shows that for a single stride, there is no
preformance drop untill I hit the 8MB L2 cache limit and it starts
accessing memory. However, if I increase the stride size I can easily
the L1/L2 cutoff at 32Kb, where it should be according to my processor
spec. Why is there no drop off visable for a single stride regardless
the data size?

Processor:
Intel Core2 Quad
L1: 256KB (128K Inst. and 128K data, or 32K per core)
L2: 8MB (4MB shared between a pair of cores)

[David L. Rager]

Think about how the hit:miss ratio with a stride size of one versus
the hit:miss ration with a large stride size.