AMD processor for Lab 4?
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Daniel Kuang
Dec 3, 2009, 11:08:45 PM12/3/09
to utexas-cs352-fall2009
Is it OK to use an AMD x86 processor for lab 4?
It says in the instructions:
"With that information, you can then lookup on Intel’s Website the
configuration of the internal caches"
Does that mean we are restricted to Intel processors?
It says in the instructions:
"With that information, you can then lookup on Intel’s Website the
configuration of the internal caches"
Does that mean we are restricted to Intel processors?
chris.heathcott
Dec 3, 2009, 11:13:25 PM12/3/09
to utexas-cs352-fall2009
The code would not run on my Opteron system, though perhaps because
I'm running amd_64 Linux rather than generic i386...
I'm running amd_64 Linux rather than generic i386...
Mhuff
Dec 3, 2009, 11:58:44 PM12/3/09
to utexas-cs352-fall2009
AMD processor should be fine...they use x86(-64) ISA...
David L. Rager
Dec 4, 2009, 12:05:47 AM12/4/09
to Mhuff, utexas-cs352-fall2009
AMD is definitely okay, and even encouraged, just so that "you" and I
get to learn about companies other than Intel.
Though, you have to obtain results that make some sense, so if the
code doesn't work on a 64 bit architecture/OS, you'll want to use
another machine.
get to learn about companies other than Intel.
Though, you have to obtain results that make some sense, so if the
code doesn't work on a 64 bit architecture/OS, you'll want to use
another machine.
chris.heathcott
Dec 4, 2009, 12:55:18 AM12/4/09
to utexas-cs352-fall2009
Yes, the Opterons are x86 compatible, but the code won't compile on
Ubuntu server amd64, probably because of the explicit target
architecture checks like "#ifdef __i386__"
I successfully compiled the code on a UTCS Linux box and on one of my
own Intel boxes, so I'm not especially motivated to hack the lab to
compile on the Opteron system, though I was curious how the latter
would compare since it has integrated memory controllers and more
memory bandwidth but much smaller on-die L2 caches.
Ubuntu server amd64, probably because of the explicit target
architecture checks like "#ifdef __i386__"
I successfully compiled the code on a UTCS Linux box and on one of my
own Intel boxes, so I'm not especially motivated to hack the lab to
compile on the Opteron system, though I was curious how the latter
would compare since it has integrated memory controllers and more
memory bandwidth but much smaller on-die L2 caches.
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