CIDER - Monday, January 21 @ 12:00pm

[Cider Seminars Admin]

WHEN: Monday, January 21, 2002 at 12:00pm
WHERE: Sandford Fleming Building, Room SF1101

"Nearest Neighbour Interconnect Architecture In Deep-Submicron FPGAs"
Ajay Roopchansingh, University of Toronto

Abstract
--------

As FPGAs become mainstream system implementation vehicles, the
desire to increase their performance is stronger. In this work we
seek to increase the speed of FPGAs by exploring the use of high
speed Nearest Neighbour (NN) Interconnections. Several
commercial FPGA architectures provide these fast connections
between adjacent logic blocks because they decrease the best-case
delay between circuit elements with the goal of increasing
overall performance. This work explores the architecture of these
NN interconnects to determine topologies, quantities and
distances that are good for performance and area. We develop an
augmented architecture generation tool and CAD flow that
enumerates and targets various portions of the NN architecture
space. We show that certain architectures can archieve a 7.7%
performance improvement at the cost of a 6.8% increase in total
FPGA area when fully populated. We also show that a 6.4%
improvement can be achieved for a more modest cost of 3.8%
increase in area.

Bio
---

Ajay Roopchansingh is an M.A.Sc. student of Prof Jonathan Rose.
His research is in the area of Architecture and CAD for FPGAs.

--
Cider Seminars Admin
<http://www.eecg.toronto.edu/cider/>