US-CA-San Jose Sr. Verification Engineer w/Video Exp

[Daniel Parrillo]

We’re
cur
ently working with a client in the Silicon Valley that is
pio
eering a low power, flexible video platform = supplying
semic
nductors, software and designs to communications and
consumer
electronics manufacturers. Our client's patented
architectur
dramatically reduces power and cost of video compression
ICs
Supporting H.264, WM9, MPEG2 and MPEG4, and leverages it’s
p
tented architecture to support multiple standards without
sac
ificing power or price.

Ideal candidate will be experienced with video compression
I
s, H.264, MPEG 2-4, etc... and the client is ONLY
interested
n "ideal candidates" !!!

Location: San Jose / Silicon Valley
CLIENT PREFERS LOCAL CANDIDATES - THERE WILL BE NO
RELOCATIO
OFFERED WITH THIS POSITION !!

Hardware design verification is one of the most important
ro
es for our client !!!! The Hardware Verification team
ensures
that their VLSI products meet the specified requirements
and
re robust in "real-world", high-volume product environments.

The Senior Verification Engineer is responsible for the
foll
wing:

* Specifying an overall design verification plan for an
ASIC

* Specifying or reviewing plans for complex blocks within
th
ASIC
* Architecting new verification methodologies, evaluating
ne
tools
* Develop new design and verification tools (including
test
enerators)
* Setting up Verilog test benches for the ASIC and major
blo
ks, and developing behavioral models for these blocks
* Managing regression test runs & debugging simulation
failu
es
* Being a mentor and technical leader for more junior
verifi
ation engineers
* Leading or participating in the lab bringup, debug, &
vali
ation of first-silicon ASICs

Requirements
* BSEE or MSEE with at least 6 years experience in Design
Ve
ification, including 2 years as a verification lead
* Extensive experience with C & C++ and Makefiles
* Experience writing Verilog-based simulation test
benches,
riting Verilog PLI routines, and running Verilog
simulations
* Excellent debug skills in a Verilog design environment
are
a must
* Proficiency in common UNIX scripting languages (perl,
csh,
sh)
* Experience using Vera or Specman test languages and
formal
semi-formal verification tools desired
* Knowledge of video standards and algorithms or
microproces
or architecture and verification
* Must have good communication skills and the ability and
de
ire to foster a team environment

For IMMEDIATE consideration, please forward a copy of your
d
tailed, chronological resume in MS Word or .RTF format to:

Daniel Parrillo
President
Strategi LLC
Phone #: 415-519-1828
E-mail:

PLEASE - NO THIRD PARTY VENDORS, AGENCIES OR CONSULTING
FIRM

PLEASE - ONLY APPLY IF YOU QUALIFY, LOCAL AND HAVE THE
QUALI
ICATIONS DEFINED IN THE JOB DESCRIPTION !!

Requirements:

BSEE or MSEE
Min 6 yrs design verificaton experience w/2 years as lead
!!
MUST have strong skills in Verilog PLI routines & Verilog
si
ulations and experienced with Vera or Spacman test languages
IDEAL Candidate will have knowledge of Video standards and
a
gorithms and microprocessor architecture and verification

Additional Information:

Job Number: JN-VerifyEng
Position Type: Full Time

Contact Information:

Email: int...@postmyjobs.com

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