US-CA-San Jose ASIC Design Engineer w/MPEG exp

[Daniel Parrillo]

We’re
cur
ently working with a client in the Silicon Valley that is
pio
eering a low power, flexible video platform = supplying
semic
nductors, software and designs to communications and
consumer
electronics manufacturers. Our client's patented
architectur
dramatically reduces power and cost of video compression
ICs
Supporting H.264, WM9, MPEG2 and MPEG4, and leverages it’s
p
tented architecture to support multiple standards without
sac
ificing power or price.

Ideal candidate will be experienced with video compression
I
s, H.264, MPEG 2-4, etc... and the client is ONLY
interested
n "ideal candidates" !!!

Location: San Jose / Silicon Valley
CLIENT PREFERS LOCAL CANDIDATES !!! RELOCATION WILL NOT
BE
ROVIDED !!

The ASIC Design Engineer is responsible for the following:

Specification, microarchitecture, RTL design, synthesis,
and
standalone verification of various blocks on SoC ASICs
Participating in the bringup of chips in the lab

Requirements

BSEE or MSEE with at least 4 years experience in RTL logic
d
sign using Verilog and industry-standard EDA tools such as
Sy
opsys' synthesis tools, static timing analyzers, and
Verilog
imulators
Experience writing C models for hardware algorithms
Experience using common scripting languages (Tcl, perl,
csh,
sh)
Prefer that the candidate has an understanding of
microproce
sor architecture and software/hardware interaction, as well
a
experience with common peripheral interfaces & buses
Knowledge of video or audio standards and algorithms a
plus
Knowledge of low-power design techniques a plus
Good communication skills and ability to work as part of a
t
am

For IMMEDIATE consideration, please forward a copy of your
d
tailed, chronological resume in MS Word or .RTF format to:

Daniel Parrillo
President
Strategi LLC
Phone #: 415-519-1828
E-mail:

PLEASE - NO THIRD PARTY VENDORS, AGENCIES OR CONSULTING
FIRM